Mux verilog työt

...comparator compares two 2-bit words, A and B, and assets outputs indicating whether the decimal equivalent of word A is less than, greater than or equal to that of word B. K-map method can be used to derive the minimized equations to describe the behavior of the comparator and Verilog module can be written to test the working of the comparator. Complete the following: o Derive minimized equations for the comparator outputs - A less than B, A equal to B, and A greater than B. Draw logic diagram. o Write and test the Verilog Module for this comparator. Provide detailed answers to the following: 1. How will you use a 3x8 decoder to build a 4x16 decoder? Draw a schematic diagram and explain your solution. 2. How will you use a 4x1 multiplexer to build a 16x1 multip...

I need two projects on VLSI design using verilog/vhdl language with complete coding and documentation.

Hi, I have a model file written in HSPICE and need to convert it into Verilog-A or Verilog-AMS. Thanks John

Hi, I have a model file written in HSPICE and need to convert it into Verilog-A or Verilog-AMS. Thanks John

...xyz’ b. ABC + A’B + ABC’ c. (x + y)’ (x’ + y’) 3. List the truth table of the following functions. Also draw the logic diagram (gate implementation of the following functions) a. F = xy + xy’ + y’z b. Y = (A + B) (C’ + D) 1. Write the canonical sum of products and canonical product of sums for the following functions: a. F = ΣX,Y,Z(0,3) b. F = ΠA,B,C(1,2,4) 2. Write Verilog code to describe the following functions: a. f1 = x1x3’ + x2x3’ + x3’x4’ + x1x2 +x1x4’ b. f2 = (x1 + x3’) . (x1 + x2 + x4’) . (x2 + x3’ + x4’) 3. A given system has 3 sensors that can produce an output of 0 or 1. The system operates properly when exactly one...

i have an fpga algorithm fully compatible for conversion to verilog. vhdl. i need some expert to define the acticture re assemble it and test it on fpga. i have some verilog implementation code for it too.

There was a phase 1 for this project it was designed and implemented using active HDL software, Verilog language. all we want is to convert the phase 1 design into magic software design (), the phase 1 is attached

I have complete Project code, It successful compile but its not showing any output, showing zero-zero. Please bid only if you are expert in Verilog.

We wrote our verily code for simulation about a Bank Queue Project. We need improvement in our Implementation on BASYS

implement 8-point FFT Architecture using verilog

Experiment need to be done and explain in logic circuit design (mux IC) using ewb v5.12 need it in 4hrs

I have code, i want to correct one file and make according to my project file, which i am attaching.

Verilog codes that fully compliant with EPC Gen2 Standard/ISO18000-6-C (RFID Tag baseband) including verification testbenches.

it is described in the file below i need this done in an hour

it is described in the file below i need this done in an hour

Verilog Morse Decoder Design  Input: Single input (only one bit(0-1))  Outputs: You should print at least one sentence(ASCII characters) to screen on Xilinx Environment. (Exp: 1 THE BEST ADVICE IS FOUND ON THE PILLOW)  Timing: Decoding a character should last at most 30 seconds. International Morse code is composed of five elemenets: X short mark, dot or ”dit” (.): ”dot duration” is one time unit long X longer mark, dash or ”dah” (-): ”dot duration” is three time units long X inter-element gap between dots and dashes within a character: one dot duration or one unit long X short gap (between letters): three time units long X medium gap (between words): seven time units long

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Hi I am looking for an expert who has in depth understanding of Tomasulo architecture for Processor , who can explain it to me in detail and also assign me a project in C/C++ or Verilog and work with me.

Need a small technical work in very log and explanation. If you have free time today then u can bid here.

...the MediaCodec/MediaMuxer classes, you are perfect for the job. Here's what we need: 1. (optional) Convert an array of Bitmaps, each with its own unique duration, into a single MP4 video (I’ve done this already with JCodec, but there may be better ways). 2. Mux an MP3 file with the MP4 video, and have control over its start point and its duration, and make it play again from its beginning if it is not long enough for the generated MP4 video. 3. Be able to trim an M4A file generated by audio recording on the device and mux it with either the aforementioned MP3 file, or the MP4 video, whichever is easier. The final output should be an MP4 video with 800 x 800 resolution, that is composed of a series of images, an MP3 instrumental, and an M4A audio reco...

Hi i need verilog expert who has cadence software. Bid here if you qualifies with the requirement. Thanks

Abstract—Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy for embedded memories. This paper proposes an efficient BISR strategy which consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible that it can provide four operation modes to SRAM users. Each fault address can be saved only once is the feature of the proposed BISR strategy. In BIAA module, fault addresses and redundant ones form a one-to-one mapping to achieve a high repair speed. Besides, instead of adding spare words, rows, columns or blocks in the SRAMs, users can select normal words as redundancy. The selectable redundancy brings no penal...

please check the details here .. My budget is 15$ and best review ============================================ if someone is efficient in php/mysql i have another task which neeed to be done online which is here in another link

Hi, This is a school's assignment. It it required to design a circuit that counts the number of ones in a 32-bit input X. The circuit has a 1-bit control input count, and a 6-bit output Y. The count input is connected to an internal controller that is used to control the counting process. As long as the count input is 0, the circuit is disabled, and the output is 0. Once the count input becomes 1, the input X is loaded into a 32-bit internal shift-register A, and the counting processes is executed. Beside I need to document the solution in a report that includes the following: 1. Problem definition. 2. At least two detailed alternative solutions. 3. Comparison of the alternative solutions. The comparison must be based on the complexity (the cost), and the scalability of the cir...

Assembly project with circuit design.

I need to design a clock using 7 segment in verilog HDL language using Active HDL app see the pics i uploaded it might help to understand what im looking for requirements: - Verlog code - waveform

Hi, I am looking for someone with experience in verilog/VHDL programming or with Electronics background to modify some code. Details and files will be given in chat in what needs to be done in the code.

Dear sir/maam, I have a job experience in VLSI design ,i am good in VHDL,VERILOG

I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'...

I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'...

We need to Implement the MIPS-L single-cycle design using Verilog that can run the R-type (add, sub, and, or and slt), lw, sw, beq, addi, j, jr and jal instructions. Notice that the MIPS-L has a reset input. If reset = 0 then the MIPS-L will run as normal. If reset = 1, then the MIPS-L has its PC value set to 0. Your test bench should instantiate the MIPS-L module and the memory. It will also generate the clock signal and the reset. It will display the outputs “pc-out”, “alu-result”, and display the contents at certain memory locations.

I have some really old Verilog code that was generated from some obsolete hardware (~30 years old, specialized and no longer made). Unfortunately this recreation took into account numerous hops done for timing... so it's pretty messy. What I would like is for the Verilog code to be cleaned up without altering the gates (so equivalent logic, just removing the confusing hops). Typically you'll see lines like A<= B | C, B<=D, D<=E, E=F, F=G, G=H in the Verilog. So I'd like that simplified to just A<= H | C. I think their are programs that can do this, I just don't have access. The easiest way to work would be from the output backwards towards the inputs. I'd also like a circuit schematic as well, preferably in a format that is wi...

Description: • Implement a 16-bit carry lookahed adder in Verilog that has 2-levels of carry lookahead. A functional (zero delay) should be used to verify circuit works properly and a nonzero simulation to evaluate performance. Structural(not behavioral) Verilog must be used. • Provided is a 16-bit ripple carry adder. Simulation and write-up: • Circuit diagram of 16-bit ripple carry adder and 16-bit carry lookahed adder • Critical path & delay of both adders under the unit gate delay model • Gate cost of both adders • Functional (zero delay) simulation results for both adders providing the Verilog implementation of your circuits work properly. Multiple data sets should be used to prove this. There should be ten data sets spannin...

I need someone who will teach me verilog from scratch. Online teaching is preferred. I will prefer at least 20 classes. The classes must include explaining diffenent types of verilog code for ADL stuffs like sequential circuit, memory, combinational circuit with test bench as well. Interested candidates please contact me. Thanks in advance.

I want to write verilog code as required my project pdf file. Please do it as it instructs the assignment pdf

...performance. Structural (not behavioral) Verilog must be used. Write up needs to be included which contains the following information: *circuit diagrams of both adders down to gate level *Critical path & delay of both adders under the unit gate delay model *Gate cost of both adders *Functional (zero delay) simulation results for the adders proving the Verilog implementation of your circuits work. Multiple data sets should be used to prove this. there should be ten data sets spanning all 16-bits of operands. *Analysis of the average delay across 5,000 randomly selected input patterns for both adders using the unit gate delay model. Specifically state how this average compares to the critical path delay. The files that need to be provided are the Veril...

ECE 171 Fall 2015 Project 2 You are to design a combinational logic circuit to determine whether a given input i s a leap year . The year input consists of four BCD digits YO, YT, ...lose 30 points. Submit your project by upload ing a single zip file to D2L containing the following: • – your project report with all design work (diagrams, truth tables, K - maps) and timing diagrams • leapyear.v – your Verilog source code for the LeapYear module • iszero.v – your Verilog source code for the IsZero module • iszerotb.v – your Verilog source code for the IsZero testbench • divbyfour.v – your Verilog source code for the DivisibleByFour module • divbyfourt...

I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'...

adder register with 2 input (i.e. A, B), Clock, reset 32 bit adder register with 2 input (i.e. A, B), Clock, reset need to use Qurtus 2 (Altera ) software Write the Verilog code for a 32-bit Adder with registered inputs and outputs Write the Testbench code in Verilog and verify your design works as intended using VCS The inputs are: reset (active low), input1, input2, clock The output port is: result

In this project we have to design the multi-cycle datapath for the modified MIPS-Lite (MML) ISA and we will model and verify your design using the Verilog Hardware Description Language (HDL).

Write a verilog to Turn off the LEDs and Seven Segment Display in Altera FPGA's boards. I need it with explanation so I can understand it

Implement a 16-bit carry lookahed adder in Verilog that has 2-levels of carry lookahead.

i need a VERILOG CODE for a FLOATING POINT MULTIPLIER DESIGN BASED ON CSD (Canonical Sign Digit)

It is a Verilog Project. Please see the attached details.

Hi, I am looking for someone with experience in verilog/VHDL programming or with Electronics background to modify some code. Details and files will be given in chat in what needs to be done in the code.

Hello, I have a simple simulation assignment, which I need a solution for in verilog code. I need it today. Thanks.

design the multi-cycle datapath for the modified MIPS-Lite (MML) ISA from homework #2 (and summarized below). You will model and verify your design using the Verilog Hardware Description Language (HDL)

It is a Verilog Project. Please see the attached details.

The inputs for the multiplier are A (A3, A2, A1, A0) and B (B3, B2, B1, B0), Reset and Start. The outputs for the multiplier are O (O7, O6, O5, O4, O3, O2, O1, O0), and Finish The operation of the multiplier is as follows 1. When Reset = 1 the system is reset 2. When start = 1 the following occurs a. Load A on the first 1 b. Load B on the first 1 c. After n cycles the output is stored in O and the Finish output is asserted d. There is no change to the output after subsequent cycles. In this phase you are to describe the HDL code that you will use and the specify the names and timing types (s1, s2, etc) for all signals used to implement the system Prepare a well organized and well written report that describes your analysis, model development, and simulation results.

...packets and loaded in a WIZ830MJ board (W5300 chip) to be sent to a computer by Ethernet network and captured in a .NET program to be recorded as raw data. All of this is done in continuous, realtime. We are talking about a lot of data to be recorded - 20 bits (maybe recorded in 24bits or 32 bits words) @ 1Mhz sampling rate. No need for encryption or compression. Moreover, there are other verilog modules running on the FPGA that will be independent of the data acquisition, but timed on the same clock. The test bed is already assembled in Canada and connected on a laptop, and can be accessed through Teamviewer or some sort of VNC in order to test the performance. There is already code that has been put in place and half-working. We are also open to other suggestions o...