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    4,943 verilog ascii työtä löytyi, hinnoittelu EUR

    I have a file with more than a million rows of data (ASCII or a flat file). I need it to be formatted and converted to and excel spreadsheet.

    €23 (Avg Bid)
    €23 Keskimäär. tarjous
    24 tarjoukset

    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

    €174 (Avg Bid)
    €174 Keskimäär. tarjous
    1 tarjoukset

    ...like it to test/create the wrapper with. The .NET std class will at lease perform a TCP & UDP socket connect/disconnect with an external system, send/receive some arbitrary ascii text data. The external system could be a simple test app built with this class also. You may build this class yourself or we can supply one, on your request. This functionality

    €513 (Avg Bid)
    €513 Keskimäär. tarjous
    9 tarjoukset

    ...(eg X00001,X00002,... X0000n). Node will transmit data based on periodicity (typically will be every minute) and as and when any input is changed. Nodes data format will be ASCII, as below: X00001,count=23,s1=0,s2=0,s3=0,s4=0,s5=0,s6=0,s7=1 Where X00001: Node ID, count= counter value, sx: satus inputs. We also need the Mobile gateway application,

    €210 (Avg Bid)
    €210 Keskimäär. tarjous
    4 tarjoukset

    ...like it to test/create the wrapper with. The .NET std class will at lease perform a TCP & UDP socket connect/disconnect with an external system, send/receive some arbitrary ascii text data. The external system could be a simple test app built with this class also. You may build this class yourself or we can supply one, on your request. This functionality

    €460 (Avg Bid)
    €460 Keskimäär. tarjous
    5 tarjoukset

    ...about.. like an ebook reader incorporated into the app. and the “&#8230” in the events .. I’m thinking that we need to check on the events areas and make sure any and all ascii characters are adjusted to real characters in the display • Library news is showing entire articles instead of just a snippet with a "Read More" link at the end. Can we d...

    €78 (Avg Bid)
    €78 Keskimäär. tarjous
    2 tarjoukset

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    €49 (Avg Bid)
    €49 Keskimäär. tarjous
    24 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €911 (Avg Bid)
    €911 Keskimäär. tarjous
    4 tarjoukset

    ...about.. like an ebook reader incorporated into the app. and the “&#8230” in the events .. I’m thinking that we need to check on the events areas and make sure any and all ascii characters are adjusted to real characters in the display • Library news is showing entire articles instead of just a snippet with a "Read More" link at the end. Can we d...

    €340 (Avg Bid)
    €340 Keskimäär. tarjous
    5 tarjoukset

    ...to these hashes. This is in C#. .The project is to create a JS function called hsh(string) and a C# function called hsh(string) .Both functions must return a readable sha1 ascii string. .Critically, if given the same input; then both should produce the same output. Note also: - In both cases all whitespace should be removed from the input string

    €162 (Avg Bid)
    €162 Keskimäär. tarjous
    15 tarjoukset

    hello, everyone i would like to hire fpga and verilog experts if you have experience on fpga, please bid on my project. thanks.

    €467 (Avg Bid)
    €467 Keskimäär. tarjous
    20 tarjoukset

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [kirjaudu nähdäksesi URL:n]; a. The source can

    €550 (Avg Bid)
    €550 Keskimäär. tarjous
    3 tarjoukset
    find fpga projects Loppunut left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    €407 (Avg Bid)
    €407 Keskimäär. tarjous
    10 tarjoukset
    Matlab Codnig Loppunut left

    I need the matlab developer and verilog developer

    €550 (Avg Bid)
    €550 Keskimäär. tarjous
    17 tarjoukset
    HTML email Loppunut left

    ...HTML email built to send to a large database. Must be Responsive, Scalable and Hybrid. The specs are: 1. Fully built HTML submitted as HTML 2. 700–pixel width maximum 3. ASCII format 4. 80k maximum file size. 5. Use inline CSS ONLY. Any formatting or font specs in the code must occur in the body of the code (no linked or external CSS "les. Do not

    €116 (Avg Bid)
    €116 Keskimäär. tarjous
    57 tarjoukset

    *** ...most recently obtained numeric values in human readable format (converted from HEX data). Most parameters are 32-bit floating point data, 32-bit Unix Epoch date stamps, or Ascii text. *** DELIVERABLES *** - Android Studio project files (project folder zipped up and emailed) - Compiled .apk file for installation onto a smartphone for testing

    €2105 (Avg Bid)
    €2105 Keskimäär. tarjous
    19 tarjoukset
    write a c program Loppunut left

    ...it initially looks if you remember how character data is really stored internally and bear in mind the ordinal properties of the alphabetic characters of either case in the ASCII table (remember you can ignore case by simply converting the entire string to all one case)....

    €56 (Avg Bid)
    €56 Keskimäär. tarjous
    50 tarjoukset

    ...Window (pc) that all pc will open it the same structure it define right now in Linux. Theis is H line with details bellow their is L line with details Need to keep align use ASCII and clean code to make it work on 3th software that will run this file and use that data to provide Document... I attached file to show how all point in L line it's in order

    €164 (Avg Bid)
    €164 Keskimäär. tarjous
    11 tarjoukset
    16-point FFT Loppunut left

    verilog code for radix-4 16 point fft

    €13 (Avg Bid)
    €13 Keskimäär. tarjous
    8 tarjoukset

    This Project is to close a workflow gap for PCB Mounting with a Pick-and-Place Machine. There is 2 larger Pieces involved #1 (ASCII) Data Transformation #2 Visually supporting Mapping of Components in KICAD to "Reels" (Components loaded into the machine) # Constraints: - Software should be developed in Python and not contain Proprietary Modules. - Copyrights

    €567 (Avg Bid)
    €567 Keskimäär. tarjous
    10 tarjoukset

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    €14 (Avg Bid)
    €14 Keskimäär. tarjous
    4 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €10435 (Avg Bid)
    €10435 Keskimäär. tarjous
    2 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €9143 (Avg Bid)
    €9143 Keskimäär. tarjous
    1 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €787 - €793
    €787 - €793
    0 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €776 - €777
    €776 - €777
    0 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €778 - €778
    €778 - €778
    0 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €789 (Avg Bid)
    €789 Keskimäär. tarjous
    3 tarjoukset

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €647 - €777
    €647 - €777
    0 tarjoukset
    reviewing a code Loppunut left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

    €46 (Avg Bid)
    €46 Keskimäär. tarjous
    1 tarjoukset

    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    €132 (Avg Bid)
    €132 Keskimäär. tarjous
    3 tarjoukset

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    €137 (Avg Bid)
    €137 Keskimäär. tarjous
    6 tarjoukset
    Verilog Expert Loppunut left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    €53 (Avg Bid)
    €53 Keskimäär. tarjous
    20 tarjoukset

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

    €31 (Avg Bid)
    €31 Keskimäär. tarjous
    6 tarjoukset

    ...for a listing of all trap vectors. You can use the pseudo-op .STRINGZ to store a string into your program. Hints and suggestions Remember, all input and output functions use ASCII characters. You are responsible for making any conversions that are necessary. Before sitting down at the computer, give some serious thought to what this program involves.

    €9 - €26
    €9 - €26
    0 tarjoukset

    ...character frequency table. Input to the procedure should be a pointer to a string, and a pointer to an array of 256 doublewords. Each array position is indexed by its corresponding ASCII code. When the procedure returns, each entry in the array contains a count of how many times that character occurred in the string. Include the source code only. Via Using

    €25 (Avg Bid)
    €25 Keskimäär. tarjous
    3 tarjoukset

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    €123 (Avg Bid)
    €123 Keskimäär. tarjous
    2 tarjoukset

    python (or any desktop a...application code) application that will: detect a material (ex. an authentication dallas key ) plugged into com port (rs232), read data from it, convert data from hexa to ascii put asci code into the keybord buffer the application will run in the background project for inspiration ([kirjaudu nähdäksesi URL:n])

    €120 (Avg Bid)
    €120 Keskimäär. tarjous
    7 tarjoukset

    python (or any desktop a...application code) application that will: detect a material (ex. an authentication dallas key ) plugged into com port (rs232), read data from it, convert data from hexa to ascii put asci code into the keybord buffer the application will run in the background project for inspiration ([kirjaudu nähdäksesi URL:n])

    €571 (Avg Bid)
    €571 Keskimäär. tarjous
    6 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €77 (Avg Bid)
    €77 Keskimäär. tarjous
    5 tarjoukset
    €23 Keskimäär. tarjous
    4 tarjoukset
    €26 Keskimäär. tarjous
    6 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €158 (Avg Bid)
    €158 Keskimäär. tarjous
    7 tarjoukset

    The program purpose > The program should: - take a sound device's input signal, eg a PC microphone - output the "volume" as ascii bars to the shell for a predefined time (eg 30 seconds) *in real-time* - "volume" here means the RMS (root mean square) of the pcm signal over a given number of samples N (that is v = sqrt(sum(s[i]^2)/N)) In order

    €141 (Avg Bid)
    €141 Keskimäär. tarjous
    14 tarjoukset

    Need help program FPGA with Artix-7 using Verliog.

    €110 (Avg Bid)
    €110 Keskimäär. tarjous
    5 tarjoukset

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    €154 (Avg Bid)
    €154 Keskimäär. tarjous
    1 tarjoukset

    Implement the Zen Protocol in the FPGA and update the Mining App

    €1074 (Avg Bid)
    €1074 Keskimäär. tarjous
    3 tarjoukset

    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    €22 (Avg Bid)
    €22 Keskimäär. tarjous
    6 tarjoukset

    Make a serial interface system using Verilog

    €42 (Avg Bid)
    €42 Keskimäär. tarjous
    4 tarjoukset

    We need the following customization work to be done for Tally. Standard Interface Files for Credit - Account Upload from ERP - Inbound Transaction Feed - Outbound Transaction Feed - Exempt Transactions – Inbound - Exempt Transactions – Outbound Standard Interface Files for Debit - Bank Branch Vendor - Customer - Account - VAT TRN Details - Transaction Input - VAT Outbound Above dat...

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    €392 Keskimäär. tarjous
    4 tarjoukset