RISC architecture (MIPS), pipeline hazards, and hazards mitigation techniques

Hi, I am digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE, and Quartus for FPGA, using DC, ICC, and prime-time for ASIC. and UVM for verification. regarding your projcet, I have worked in many projects related to MIPS, currently I am working on a 7 stage pipline MIPS which uses a hazard unit and a forwarding unit to manage hazards. I will provide you with a clear explanation of each part of the code, and I will teach you how to make it yourself I can deliver in a week or 10 days max Please contact me to know more about your needs. Regards, moaaz.

I have done piplined mips with hazard unit. Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and others.  Please contact me to discuss more about this project. Kindest regards.

Hi Dear! I am an expert in C, C++, Algorithm, Assembly, ARM, Embedded System. I already check your description with carefully and very interesting your project. Specially I have more than 25 years of experience in software development. If you give this project for me then you can get wonderful result on time. Hope to meet in chat box for will discuss more about project. Looking forward to hearing your reply. Thanks. From James.

Hello. As a Masters graduate, I've done a lot af designing/modifying of MIPS architecture and I am quite an expert when it comes to MIPS architecture. Also I am an expert C/C++ programer with more than two decades of programming experience. So practically speaking this is a piece of cake Best regards