Suljettu

Asic Design / FPGA

15 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_26% %project_currencyDetails_sign_sub_27% tähän työhön

ahmedmohamed85

A proposal has not yet been provided

$275 USD 2 päivässä
(337 arvostelua)
7.7
raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Relevant Skills and Experience Verilog/FPGA - 3+ years Proposed Milestones $6 Lisää

$133 USD 3 päivässä
(54 arvostelua)
5.8
uetian09ee506

Hi, we can chat regarding your project Relevant Skills and Experience Electrical Engineer Proposed Milestones $77.5 USD - Milestone 1 $77.5 USD - Milestone 2

$155 USD 3 päivässä
(31 arvostelua)
5.0
$200 USD 3 päivässä
(17 arvostelua)
4.1
kulwantsingh16

A proposal has not yet been provided

$90 USD 3 päivässä
(14 arvostelua)
4.2
jasnaikaran

Hello, I am an electronics engineer having experience in FPGAbased system design for more than 5 years. Relevant Skills and Experience VERILOG/VHDL, FPGA, Electronics Proposed Milestones $55 USD - Verilog Code

$55 USD 2 päivässä
(6 arvostelua)
3.2
$100 USD 3 päivässä
(6 arvostelua)
3.1
ReconLogic

Hi! I am professional FPGA developer in Germany and proficient in Altera tools and FPGAs. I can develop a clock according to your board and specs with available user interfaces designs too. Relevant Skills and Experie Lisää

$333 USD 10 päivässä
(3 arvostelua)
2.9
$50 USD 5 päivässä
(2 arvostelua)
2.6
nikj1101

hey, I'm experienced in Verilog and VHDL. I've worked on quartus. please get back if you need help

$132 USD 3 päivässä
(1 arvostelu)
1.0
jenistenalbert

My handful experience in Verilog HDL coding will help me to design digital clock for you. I have implemented softcore processors in Quartus tool that will help me to complete this project. Relevant Skills and Experien Lisää

$55 USD 10 päivässä
(0 arvostelua)
0.0
$155 USD 3 päivässä
(0 arvostelua)
0.0
LubaTovbin

I'd be happy to do this project. Relevant Skills and Experience I'm experienced in FPGA Design with Quartus tools. Proposed Milestones $38.5 USD - Block scheme in 4 days $38.5 USD - full RTL description in Verilog in Lisää

$77 USD 7 päivässä
(0 arvostelua)
0.0
hammadsamikhan

I am 4+ years experienced in Fpga IP core development.I can develop it at very low cost.

$35 USD 3 päivässä
(0 arvostelua)
0.0
$155 USD 3 päivässä
(0 arvostelua)
0.0