Given the following block diagram design and analyze each of the interface circuits. Determine all power ratings for all resistors. Properly terminate the busses. Do not forget bypass capacitors. You need to determine which types of capacitors, tantalum,

Given the following block diagram design and analyze each of the interface circuits. Determine all power ratings for all resistors. Properly terminate the busses. Do not forget bypass capacitors. You need to determine which types of capacitors, tantalum, ceramic, electrolytic. The choice should be justified. All resistors must be the from the following values: The block diagram above gives a general overview of the pieces. You as the designer will have to decide what signals route onto/off the card to control motor described in the DAC section. With the tachometer in the closed loop system estimate the control BW, the closed loop BW and the ideal control BW. With the tachometer in the system, how does this affect your control? Assume the controller and plant is estimated by the plant used in the control BW example from class. For this model, you will need to estimate the time constant for the plant and controller. Using the data sheet for the tachometer you have chosen estimate the BW of this sensor. If you need to add a filter include this as well in the control loop. Assume the DAC drives a motor and that you are controlling the speed. Find the control BW given an approximate model for the motor and based off your choice of tachometer. For the A/D, assume a 16 bit A/D. Include the circuitry to interface this to each of the separate analog signals. If needed use an analog MUX. For the DAC, assume a 10-14 bit resolution. Design the circuit using commercially available off the shelf (COTS) 10-14 bit DAC of your choice. . For the signal conditioning section, all signals need to be properly amplified/attenuated to work correctly with the ADC and DAC. If needed on any signals use proper filtering on the signals. Perform offset error analysis for all amplifiers and filters. For power supplies for op-amps assume that you have available +/-18V unless the op-amps you choose have smaller maximum supply ratings. Any op-amp circuits should consider gainbandwidth product as well as slew rate in the design. Assume the 3.3 V and 5V (digital) and 5V (analog) supplies are also available for digital or analog circuits. Other Inputs/Outputs (Each should be filtered /amplified as needed) : 1. potentiometer reading from -3.1 - +Vname DC, read by ADC 2. sinusoidal signal, amplitude 0-8.2 V frequency range 65 Hz to 2.7*Vname MHz and amplitude -2 –3.1V in the frequency range 4*Vname – 5*Vname MHz, read by ADC Assume 60 Hz signal with magnitude 2 is corrupting the input Signals above 2.7*Vname MHz and less than 4*Vname MHz should be attenuated. Anything above 5*Vname Mhz should be attenuated. 3. Resolver to Digital in conjunction with an oscillator to track information from a motor shaft (such as AD2S99 and AD2S90) check for more information on resolvers (MT-030: Resolver to Digital Converters by Walt Kester, Analog Devices, 2-21-06) 4. temperature sensor and interface circuit that can sense temperatures in range from -2*Vname C to 5*Vname C, output should be connected to the ADC or FPGA. Vname1 = Average of the first two letters of each of the first and last names of each person in the group, assuming A=1, B=2, C=3, D=4, E=5, F=6, G=7, H=8, I=9, J=10, K=11, L= -12, M=13, N=-14, O=15, P=-16, Q=17, R=18, S=19, T=20, U=21, V= -22, W=23, X=-24, Y=25, Z=-26 If Vname1 < 0, Vname = (Vname1+26.3)/0.9 else Vname1 < 4, Vname = (Vname1+18.3)/1.1 else Vname1 < 8, Vname = (Vname1+14.3)/1.2 else Vname1 < 12, Vname = Vname1+9.3 else Vname1 < 16, Vname = Vname1+2.3 Clock Assume the appropriate clock frequencies are available. FPGA Assume the VHDL code to generate the control signals will fit into a Xilinx XC4VFX140. You do not need to write the VHDL.