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Digital Design Electronics Verilog / VHDL
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Dragisa S.

@hdlveca

4.6
9

4.0

4.0

100%

ASIC Design Verification Engineer

$10 USD / Hour

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Serbia (4:42 AM)

Joined on November 3, 2008

$10 USD / Hour

I have been working for veriest types of IP Core Development in Verilog/VHDL. Build Verification environments in eLanguage (Specman) and System Verilog with UVM.

4.6 · 9 Reviews
9 Reviews
Y

Former Client (inactive)

5.0

$80 USD

14 years ago

Translate VHDL files to Verilog

Thank you for the brilliant work :) Great! Very friendly, and nice person to deal with. Definitely know what he has to do.very good communication. definitely would hire again.

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Mohammed Abdul Khaled S.

4.0

$85 USD

17 years ago

VHDL assignments

Rating: 4.0/5.0

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Certifications

F

Foundation vWorker Member

Verifications

On time

100%

On budget

100%

Accept rate

100%

Repeat hire rate

11%

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