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EXPLORE
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$2 USD / Hour
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Sweden (5:37 AM)
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Joined on July 20, 2007
$2 USD / Hour
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I have more than 5 years of experience in designing embedded system on various embedded platforms and technology. I have experience in designing embedded electronic systems for Communication Systems, Power electronics Control, Data security, Digital Control Systems, Digital Signal Processing.
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Education
Chalmers tekniska högskola
2008 - 2011
•
3 years
Masters
Sweden
2008 - 2011
•
3 years
University of Engineering and Technology, Taxila
2003 - 2007
•
4 years
Electrical Engineering
Pakistan
2003 - 2007
•
4 years
Qualifications
Chip Designing
2008
Skill Development Council
A Intensive course on system design using FPGA.
2008
Measurement and Control using Labveiw and PC
2010
Gothenburg university
2010
Real time Operating System with Microcontrollers
2010
Gothenburg University
2010
Publications
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor
Proceedings of Euromicro Conference on Digital System Design (DSD), p.p 675-680, sep-2010, Lille, France
A proven approach to increase performance of general-purpose processors is to add hardware accelerators. In its basic configuration, the FlexCore processor has a limited set of datapath units. But thanks to a flexible datapath interconnect and a wide control word, the FlexCore datapath is explicitly designed to support integration of special units that, on demand, can accelerate certain data-intensive applications. We present the integration of a versatile accelerator for several Cyclic Redundancy Checking
.Viterbi Accelerator for Embedded Processor Datapath
IEEE International Conference on Application-speci c Systems, Architectures and Processors July 9-11, 2012 Delft, Netherlands
We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor datapath. We investigate the accelerator's impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall en
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