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Suchitra S Bhide Email: Phone: [login to view URL] OBJECTIVE: Highly skilled ASIC Front-end engineer seeking an opportunity to use my experience in design, development and full chip verification SYNOPSIS - 7.5 years experience in complex verification environment development, full chip verification, micro architecture and RTL design. - Quick learner, very productive, can identify opportunities and solve critical issues. - Excellent leadership, interpersonal and communication skills. - Always recognized as a good and enthusiastic team player. SKILLS SUMMARY Domains: Domain Technology Work Experience Wireless Communication WLAN 802.11 Worked on full chip verification of WLAN MAC’s and SOC’s Interface I2C, SPI,USART,PCI,USB Worked on implementation of I2C SPI and USART with PIC 18F6X20 Worked on PCI Verification component in VERA Worked on USB OTG verification Networking FC, SONET,SDH Worked on FC verification component in VERA Worked on SONET and SDH eVC. Tools and languages known: Skill Name HDL Verilog VHDL HVL e VERA/ system verilog (preliminary) Testbuilder(C++) Simulators Modelsim NCSIM Synthesis Tools (preliminary) dc_shell Loenardo spectrum Configuration Management CVS, clearcase, DesignSync Waveform Debugger Verdi Signalscan Simvision Programming Language C C++ X86 Assembly OS Linux Windows Solaris PCB Design/Schematic editor Protel Orchad FPGA/CPLD Design Xilinx Foundation, Xilinx webpack tools. EXPERIENCE DETAILS Conexant Systems Pune: Blade Blade is an SOC that can act as a standalone client. The main purpose of this device is to target the embedded market that needs low power operations. Its based on ARM11 architecture with AXI and AHB- lite buses used for intra- module communication. Responsibilities: • WMAC eVC development Responsible for architecture of WMAC eVC that would generate WMAC frames and check for WMAC standard protocol violations. This was a eRM compliant eVC that would be used for verification of any WMAC device. • AXI to AHB bridge verification. Responsible for configuration of AXI and AHB eVC’s for the bridge and do a coverage driven verification. Implemented a scoreboard that had a predictor. This predictor would predict the number of AHB transfers from the current AXI transfers and complete data checks accordingly. If error would occur on the AHB then the equivalent burst would be deleted from the AXI side and the scoreboard would move ahead for next check. The scoreboard also recovers automatically when mismatch occurs and continues with data checking. Tools: Simulator : NCSIM Verification : Verilog, Specman OS : Linux HDL : verilog Other : Designsync Katana Katana is a SOC that can act as a standalone AP or client with various interfaces like PCI-e, USB, SDIO, Ethernet etc. Basically it is a router that routes Ethernet, PCIE, SDIO or DSL traffic onto wireless LAN. It supports 802.11n standard. Based on ARM11 architecture with AXI and AHB- lite buses used for intra- module communication. Responsibilities: • Stress test Setup of stress environment that imitates the traffic generated by nine AHB masters and an AXI master to test the interconnect latency and priority logic. All the masters were AHB eVC’s. The environment was made such that the masters could be configured as RTL masters or dummy eVC masters for each testcase. This enabled the testing of each RTL module in the whole SOC environment. • Verification of power islanding and pin muxing. Tools: Simulator : NCSIM Verification : Verilog, Specman OS : Linux HDL : verilog Other : Designsync Infineon Technologies India Pvt Ltd. DVBH DVBH is a single chip solution for Digital video broadcast. It is an integration of demodulator and tuner. It consists of ARM7 processor with DVBH IP from a third party vendor of Infineon Responsibilities: • RTL coding and verification for the reset controller module. • RTL coding for the port control logic(PCL) Tools: Simulator : Modelsim LE v5.8 Verification : VHDL, specman OS : Solaris HDL : VHDL Other : clearcase sgold3e S-GOLD3e is a GSM/EDGE single chip baseband IC containing all digital functionality to carry out all necessary base-band signal processing of a cellular modem. When applied as application enhanced modem, the SGOLD3e provides multimedia extensions to enable today’s and future feature phone applications. S-GOLD3e is powered by an ARM926EJ-S CPU and a TEAKLite DSP core. It is a multiple layer AHB architecture having 5 AHB buses and 3 other Infineon proprietary buses. Responsibilities: • RTL design and verification I2S Module wrapper • Integration and changes to DSP sub-system • S-GOLD3e is a derivative of already existing S-GOLD3 with two major differences. In SGOLD3e all the analog components were moved out of the chip and the chip was designed in 65nm technology. • Responsible for removal of these analog modules and stitch the DSP subsystem. • Ownership of DSP sub-system • Validation of DSP sub-system was done using VHDL environment. Tools: Simulator : Modelsim LE v5.8 Verification : VHDL, specman OS : Solaris HDL : VHDL Other : clearcase SASKEN Communication Technologies Ltd Bangalore SASKEN is one of the leading telecom service provider companies in India. It was awarded as one of the best places to work. As the part of semiconductor business unit in SASKEN I worked with its client USB- OTG device verification Microchip is a well known for its PIC series of microcontrollers. The PIC24FJ256GB110 family addresses the high end of the PIC24 market. The device contains a USB-on-the-Go interface that can act as both a host device as well as OTG. At sasken the task was to verify the USB OTG interface at the full chip level. Responsibilities: • As a project lead was responsible for making sure that the whole team completes the tasks in time. Interacted with microchip Bangalore and Chandler teams to co-ordinate the day-to-day activities. • Test plan development for verification of the USB module. • Enhancing the BFM to support device mode and BVCI interface. • Responsible for development and verification of ping-pong buffer tests Tools: Simulator : Modelsim LE v5.8 Verification : Verilog, Assembly OS : Solaris HDL : Verilog Other : CVS UMA3.2 UMA stands for Unified Megacell Architecture. This is DSP sub system for 3D mobile applications that goes into TI’s single chip mobile solutions. The DSP sub-system is composed of a C55xDSP processor. It includes Level1 memory subsystem with data and instruction cache, memory controller and system controller. Level 2 memory sub-system including unified instruction and data cache, L2 ROM and a dedicated paging logic module for address translation. It also integrates a L2 interrupt controller, system controller. Responsibilities: • Lead of the project responsible to all the deliverables from sasken side. • Test plan development for L2 ROM, L2 Interconnect and L2 MSS. • Development of UMA 3 .1 eVC UMA 3.2 was a wrapper of L2 memory and some other peripherals over UMA3.1. This eVC was developed to enable random generation of stimulus at the UMA 3.1 interface. Tools: Simulator : Modelsim LE v5.8 Verification : VHDL, Specman OS : Solaris HDL : VHDL Other : clearcase Abilene Abilene is an SOC containing an on-chip MIPS microprocessor, the Bandspeed 3-channel WLAN MAC/BB/AFE system, dual Ethernet MAC’s, and other miscellaneous system peripherals, for the implementation of multi-channel WLAN AP's. The internal modules communicate with each other on AMBA bus. Responsibilities: • Micro-architecture definition of interrupt controller • RTL coding for interrupt controller Tools: Simulator : Modelsim LE v5.8 Verification : specman, verilog OS : RedHat Linux v7.3 HDL : Verilog Other : C++, PERL, design compiler Nueces Nueces is a single chip solution for wireless network’s multi access point. It contains three wireless LAN AP’s that conform to ISO/IEC 802.11 standard and also support 802.11i (enhanced security) and 802.11e (enhanced Quality of services) standard. The chip contains two customized processors viz. Bit stream processor (BSP) and sequencer (SEQ) along with FIFO’s and other bit wise modules called processing elements (PE’s). The SEQ has a pci interface that communicates with the host through pci bus and the bsp communicates with the base band. Responsibilities: • Coding for top level wrapper shell script and PERL script which controls the whole flow of verification • Coding for regression script. • Identification of test cases and development of simplan for NAV, IFS, and fragmentation related functionality of Nueces. • Testcase development and regression debugging for NAV and IFS test cases. • Coding for part of host driver that generates the station table entries for CCMP, TKIP and WEP • Debugging of firmware for bug fixing Tools: Simulator : Modelsim Verification : TestBuilder OS : RedHat Linux v7.3 HDL : Verilog. Other : C++, PERL eInfochips limited Ahmedabad SDH eVC for Mahai Networks, CISCO, etc SDH (Synchronous Digital Hierarchy) is a standard for network communication. It mainly is designed to suffice the need of high bandwidth needed for broadband communication. This project was related to development of SDH eVC compliant to ITU-T standard. The eVC is design to be eRM (eVC reuse Methodology) compatible, with distinguishing features like: • Self checking test environment • Automatic frame generation as per constraints given by user • Selective scoping of the frame. • On the fly constraining of pointers and on the fly error injection • On the fly data addition into the frame to give exact simulation of real environment. Responsibilities: • Involved in defining the architecture of the eVC. • Coding of the module Analyzer (receiver). Tools: Simulator : Verilog-xl Verification : specman OS : Solaris HDL : Verilog Others : PERL, CVS FC VIP Fiber Channel Verification IP development the IP contained FC0, FC1 and part of FC2 functionalities. Responsibilities: • Defining architecture of VIP. • Coding for class eC_Responder. • Configuration memory and data memory management classes. Tools: Simulator : Modelsim Verification : specman OS : Solaris Others : CVS 802.11 MAC controller The task was FPGA realization of MAC layer for 802.11b station. 802.11 is a standard for wireless LAN from IEEE. The MAC supported 10 stations and was capable of working in both IBSS (Independent Basic Service Set) and BSS mode. Responsibilities: • Module Level Verification: Module level verification of modules like MH (Message handler) RXFIFO, TXFIFO, SYU (synchronization unit). The verification environment was in Verilog and Perl. • Rigorous testing of all modules and integrated MAC. Tools: Simulator : Verilog-xl Verification : Verilog OS : Solaris HDL : Verilog Others : PERL, CVS eInfo cpu core eInfo cpu core was a 8 bit cpu core that had combined all the good features of 8051 and Motorola 6800. It had an build in DMA programmable timer and pipeline instruction stages. Responsibilities: • Module Level Verification of timing and control unit. • RTL for timer module • Synthesis of the whole design Tools: Simulator :Verilog-xl Verification : Verilog OS : Solaris HDL : Verilog Others : PERL, CVS. Leonardo spectrum PERSONAL INFORMATION Marital Status : Married. Date of Birth : 29-04-1978 EDUCATION Diploma in VLSI Design from ICIT Pune in the year May 2001 B.E (Electronics) from P.V.P.I.T College Of Engineering, Budhgaon, Shivaji University in the year 2000. Degree (Year of Passing) Institution Marks obtained % Course in VLSI Design University OF Pune 67.67 B.E. (1999 – 2000) P.V.P.I.T (Budhgaon) 67.67 H.S.C. (1995- 1996) Willingdon College Sangli 86.33 S.S.C. (1993- 1994) Emmanuel English School Sangli 83.28 Other Achievements • Was selected in the leadership development program called Pegasus to enhance project management qualities at eInfochips. • Winner of two gold, two silver and one bronze medals for short story writing at National level from Uncle Babji’s Child Art Club. • Involved actively in student welfare organization called ELISA. Leaded many social activities like organizing Gathering, trekking etc on behalf of the organization