Regie B.

• 11 years of solid Design Verification experience. • Experience with pre-silicon verification of design blocks for FPGA, SoC, ASIC, and IP development. • Experience with full cycle verification: from testbench planning and architecture design, identification and implementation of testcases, coding of testbench components, debugging and regressions, up to generation of functional and code coverage reports until project reviews and sign-off. • Manage and own block level verification activities which includes schedule and deliverables. • Build constrained-random and coverage driven verification environment using SystemVerilog and UVM. • Plan the verification of design blocks by understanding and reviewing the design specifications and confidently interact with design engineers to clarify and identify important scenarios. • Debugging of test cases in RTL and Gate-Level Simulations and work well with design engineers in tracking and fixing bugs in the design. • Experience with usage and integration of 3rd Party VIPs to existing testbench platform. • Initiate creation of processes that can help improve productivity and knowledge transfers. • Mentor and train newly hired engineers and interns. EDA Tools: Cadence Xcelium, Incisive, SimVision, Synopsys VCS, VirSim, Bugzilla, JIRA, Git, CVS, ClioSoft SOS HDL/HVL/PL: Verilog, VHDL, SystemVerilog, UVM, OpenVera, RVM, C, C++, Perl Standards: PCI Express, I2C, SPI, DSP, SerDes, PCS