Käyttäjän olegkaravaev84 profiilikuva
Maan Russian Federation lippu Одинцово, Russian Federation
Jäsen alkaen 4. kesäkuuta 2015
0 Suositukset


Online-tilassa Offline-tilassa
VHDL, Verilog, FPGA (Altera, Xilinx), ASIC, C# More than 10 years of experience I Have experience in a video processing, high-speed interfaces, DDR, some exp in DSP and embedded design (C/C++) including RTOS. I have experience in C#: I participated in the design of HDL simulator as part of the End-to-End Design System
$15 USD/hr
3 arvostelua
  • 100%Suoritetut työtehtävät
  • 100%Budjetin mukaisesti
  • 100%Ajallaan
  • 33%Uudelleenpalkkaamisaste


Viimeaikaiset arvostelut

  • käyttäjän Muhammad K. kuva Project for olegkaravaev84 -- 2 $195.00 USD

    “He is the best very professional and have master skills on FPGA and Digital designing. He always deliver before due data. His dose his tasks more better than my expectation. Will definitely hire him in coming task”

  • käyttäjän reactive kuva 6522 VIA and AY-3-891x Sound Generator Project For Retro Sound Card $300.00 USD

    “Very good with updates and evaluating the details of the project. Very knowledgeable with with HDLs, Xilinx ISE, and ChipScope. Very easy to work with and communicate with. Wish I could find 5 more like him!”

  • käyttäjän Muhammad K. kuva Communication System Fpga Implementation €95.00 EUR

    “Olegkaravaev is the best. Did an excellent job. An expert in digital designing have very strong technical hold. will surely rehire him in near future.”


Senior Digital Design Engineer

Apr 2017

RTL-design. Design of the project specification, rtl-model implementation, interaction with co-executors (asic topology desiners), interaction with verifiers.

FPGA Design Engineer

Feb 2016 - Mar 2017 (1 year)

FPGA design. Video processing, receive and transmit by LVDS lines (mostly Camera Link, and some others device-specific protocols). Design a software for Nios II to manage the processes of receiving, processing and transmitting video and also for testing a prototypes. Synopsys design constraints (for multiple clock domains). FreeRTOS for Nios II. Developing a documentation for a designed modules. Experience with DVI-transceivers and with the CameraLink To DisplayPort Converter NCS8801.

FPGA Design Engineer

Sep 2013 - Apr 2014 (7 months)

The implementation of the HDR-video algorithm in FPGA (the Arria V Starter Kit was used). It included: receiving video from camera, video processing according to an algorithm, transmitting processed video to the PC for a verification (it was mine application designed on C# in MS VS). DDR3 was used for buffering.

C# Programmer

Jul 2010 - Feb 2016 (5 years)

articipation in the CAD project "Delta Design". Began as a consultant, a tester, and an expert in a digital design engineering. Starting at the end of 2013 - C# Programmer. Achivements: - RTL-models of Atmega128, all 1st generation of MSP430, PIC32. It all was designed for test the HDL-simulator of the designed CAD. - HDL simulator Simtera. Delta Design, End-toEnd Design Environment: [login to view URL]

Digital Design Engineer

Aug 2006 - Jul 2010 (3 years)

FPGA / ASIC Design. Some experience with the Encounter Cadence. RTL-models of MIL-STD-1553 controller, i2c, UART, SPI, reset and clock controller, DMA, SoC based on the CPU Leon3 with a peripherial modules of CAN, UART, MIL-STD-1553, SPI, Ethernet, DDR2 controller. FPGA prototyping. Development a documentation for a designed modules in accordance with State Standards.

FPGA Design Engineer

Jan 2004 - Jan 2011 (7 years)

FPGA / ASIC Design. Remote job. I2S, Huffman decoder. MPEG2 transport stream demultiplexer. Debugging my modules included in the developed SoC. Also developed a some simple firmwares for their CPU Termite for testing.


Specialist degree (Master of scince)

2001 - 2007 (6 years)


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