Käyttäjän gaihrekrishna profiilikuva
@gaihrekrishna
Maan Nepal lippu Kathmandu, Nepal
Jäsen alkaen 6. lokakuuta 2013
2 Suositukset

gaihrekrishna

Online-tilassa Offline-tilassa
I am instructor of 12 different courses on FPGA, VHDL, Verilog, MATLAB, HLS, PYNQ at Udemy having 2700+ Students [[login to view URL]]. I am working on FPGA design since 5 years. I have expertise on FPGA Design with VHDL, Verilog, Python, OpenCL & Tcl. I have Tools experience of Xilinx VIVADO, ISE, VIVADO HLS, VIVADO SDK, SDSoC and Device experience of Xilinx Spartan, Zynq, Kintex and Vertex 7 Series and Ultrascale FPGA.I have skills on PYNQ development, Signal processing & Machine learning/Neural Net [login to view URL] can also contact me @ . Featured FPGA Projects: +Video/Image Processing with VHDL/Verilog and High Level Synthesis +Crypto Algorithm Implementation on FPGA +Tcl Scripting for FPGA Design +PCIe based FPGA Implementation +AES IP Design and Implementation on FPGA [128,256 bit] +FMC HDMI CAM module interfacing with ZedBoard FPGA -FPGA Hardware (i have): ZedBoard,Zybo, Pynq, Nexys 4, Nexys 2, Spartan 3E, FMC-HDMI-CAM Module form Avnet.
$18 USD/hr
1 arvostelu
1.4
  • 100%Suoritetut työtehtävät
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Portfolio

Viimeaikaiset arvostelut

Kokemus

FPGA Research Lead

Jun 2017

Working on FPGA Development with VHDL, Verilog, HLS, MATLAB with Tools Xilinx VIVADO, HLS, SDK, SDSoC, SDAccel. I have expertise on Embedded System Design with Xilinx Zynq FPGA, Video Processing with Zynq, Machine Learning with FPGA, PYNQ Development, IP Development, Complete System Deployment on AWS, Nimbix and Plunify FPGA based Clouds.

FPGA Design Engineer

Jan 2013 - May 2017 (4 years)

FPGA Design with VHDL/Verilog/Tcl and Xilinx Tools/Hardware

Koulutus

M.Sc Engineering

2013 - 2015 (2 years)

Pätevyydet

FPGA Trainer (2016)

Digitronix Nepal

FPGA Training with Spartan and Zynq FPGA for Industrial and Academic Professionals.

Julkaisut

Online Course on Embedded System Design with Xilinx Zynq FPGA and VIVADO

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Course instructor of VHDL Programming and Verilog Programming

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ARM Based Computing Technology for SD

IOE Graduate Conference 2015

High Level Synthesis based FPGA Design-Online Course at Udemy

It explaines about the HLS design methodology, HLS optimization, Generating IP from the HLS Design, How to create testbench on HLS, C/RTL Co-simulation etc. I also have included some real time example of Video/Image Processing in this course! I have showed up the Sobel Edge Detection algorithm on HLS and created the complete VIVADO project for it. Then tested on the Xilinx Zynq FPGA: [login to view URL]

Face Detection and Recognition with PYNQ FPGA

The Face detection and recognition algorithm is implemented on the PYNQ FPGA. The VIVADO based overlay and Python methodology for face detection and recognition is followed on the PYNQ FPGA Board.

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