SoC design/verification engineer

$50 USD / Hour

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Romania (5:43 AM)

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Joined on October 3, 2008

$50 USD / Hour

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Xilinx (7 series), ZYNQ UltraScale+ FPGA programming platforms; Vivado, Vivado HLS, Xilinx SDK, Xilinx System Generator MATLAB/Simulink, SDSoC tools; Verilog, VHDL (beginner), SystemC (including synthesizable version), C/C++ languages;

Verifications

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Portfolio

9400271

My resume

9400268

ModBus for real-time systems implemented as a hardware Cntr

9400264

PID software algorithm implementation

9400259

PID implemenntation as hardware block

4737021

Implementing a HLS CNN for digit recognition

4620104

Implementing a Hardware RTOS over a RISC V architecture.