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Radar data acquisition through LVDS in Avnet Ultra96 - VHDLApr 2019 - May 2019 (1 month)
Radar data from TI's IWR1642 development board acquired through the High Speed ports of the Zynq Ultrascale+ MPsoC in the Ultra96 board. The data transfer protocol used is LVDS.
1-Wire Device controller for TEDS - VHDLOct 2018 - Nov 2018 (1 month)
A controller to act as master to read a set of 1-wire PROM devices for TEDS data. The data is collected and forwarded to software
Multi-threaded application on a system with 32 processor cores - C++Apr 2018 - Jun 2018 (2 months)
An arcade game was implemented on a 32-core processor real-time system that was deployed on a Virtex 7 FPGA, which worked at 60 fps.
32-bit processor - VHDLMar 2018 - Apr 2018 (1 month)
A processor for a subset of MIPS ISA which was tested using assembly programs
Machine code instruction verifier - PythonJan 2017 - Feb 2017 (1 month)
A Python based program to verify a tool-generated machine code against an assembly instruction schedule.
Network packet classfier - VerilogJan 2017 - Mar 2017 (2 months)
An FPGA based module to classify network packets based on header details, which was capable of handling a link at 10 Gbps in real time.
FPGA based Network Security Engine - VerilogAug 2015 - Apr 2016 (8 months)
The Network Intrusion Prevention System (NIPS) was made to be able to process a subset of the open source Snort rule set for detecting known network attacks. It was capable of analyzing a link at 1 Gbps in real time.
Overall Band Score: 8.5
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