[url removed, login to view] : Web application to create VHDL & Verilog test benches
Hotbench ([url removed, login to view]) is allow-cost test bench generation web-application. It helps engineers to intuitively create test bench with by using mouse clicks.
The application is fast and support both VHDL and Verilog HDLs for generating test bench.
Web-based application makes the tool unique in overcoming geographical boundaries and OS (platform) independence.
User management/GUI and login IDs for user ensures security.
The web application allows HDL users to login and select for HDL options from VHDL/Verilog.
And then enter the entity/module declaration that contains IO ports for their Unit Under Test (UUT).
The users then select for best patterns in order to test & verify their designs. The web application allows user then to download simulation ready test bench.
The generated code is transparent, thus users may wish to alter to fine tune his verification needs (e.g. system_clock etc).
* Ideally helpful to freelancers/freelance developers/professionals those are working with HDLs, Educational/Academic institutions & in turn students. Small & medium scale industries, product/turnkey service companies.
THIS IS A SALES PROJECT.
AIM IS TO SELL SUBSCRIPTIONS (SHORT/LONG TERM).
BIDS ARE EXPECTED TO HIGHLIGHT THEIR POTENTIAL MARKET.
Target are freelancers/freelance-developers/professionals those are working with HDLs (vhdl/verilog), Educational/Academic institutions & students etc.
11 freelancers are bidding on average $127 for this job
I'm an expert in VHDL and Verilog. I have about 4 years of experience in Verification projects and involved in creating different types of test benches. Please consider my bid.
Solution will be designed in PHP, an extendable solution is prevented that will be able to support VHDL/Verilog/SysmteC testbenches. Reset duration and clock period is configurable.