VHDL / FPGA Development

to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations:

• The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player runs out of time.

• The second mode of operation should be a game clock variation of your choice.

You should produce a report (maximum 1500 words, excluding appendices), in pdf format, that gives a comprehensive account of the design process including the hardware setup, VHDL code testing and evaluation. It should also include:

• Instructions for the user.

• The full set of VHDL files in an appendix (code excerpts may also be used in the main body of the report to illustrate a particular point).

• Relevant references where appropriate.

Taidot: Verilog / VHDL, FPGA, FPGA Coding

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Projektin tunnus: #29456517