I am a senior PhD Level Expert and Have more than 5 years of experience in electronics and embedded design, fpga, verilog/VHDL.
Just check my profile and share your details.
Time and Budget will be discussedLisää
I am expert in VHDL with more than 7 years of experience in implementing complex to medium designs. I will be able to implement the ARINC429 decoder on Spartan 6 or 7 FPGA. The written code will be best in terms of resLisää
Thank you for taking time to read my proposal. You are welcome review my profile to know more information.
I have 4 years of experience in VHDL. Im familer with making counter, up counter , download counLisää
I have done projects involving complex packetization and parsing including 10G/100G UDP/IP Offload Engine which includes packetization/de-packetization of multiple layers. So , I believe I can delivery your worLisää
I am available right now for the project discussion and can start the project
on an immediate basis. I have understood your project requirement
I have7++ experience in design and development. I can haLisää