Verification of MESI protocol using System Verilog and UVM

MESI is a cache coherence protocol. The verification of the protocol is to be done using System Verilog and UVM. The signals to verify is sent through the sequencer to the driver and through the virtual interface to the DUT. The assertion checks should be written in the testbench.

Taidot: Verilog / VHDL, Simulation, Very-large-scale integration (VLSI), Front-end Design

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