Instructions: Include the code and test results for the following problems.

1. Draw a schematic of a half adder (obtain the simplified Boolean expression

from the truth table and K-maps) using Xilinx ISE WebPACK and show the

half adder diagram and implementation too.

2. Use a conditional statement (if-else) to develop the Verilog code for a 2 to 1

multiplexer and run the behavioral analysis using Xilinx ISim.

3. Develop the Verilog code for a NAND module using case statements.

Develop the test bench and include $display tasks to indicate the outputs

on the console window.

4. Develop the Verilog code for a full adder module using and, or and xor

primitives. Develop a test bench using a “for” loop and run the behavioral


Taidot: Verilog / VHDL

Näytä lisää: vhdl and verilog, use of use case diagram, use case diagram problems, use case diagram of, use case diagram include, the use case diagram, statement of the problems, draw use case diagram, draw use case, xor, xilinx, webpack, verilog vhdl, nand, microprocessor 2, ise, behavioral, loop table, bench, code using nand, vhdl code, vhdl xilinx, draw diagram, multiplexer code, code multiplexer

Tietoa työnantajasta:
( 30 arvostelua ) BEAVERCREEK, United States

Projektin tunnus: #4251417