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FPGA design with Verilog

Introduction

In this assignment, you will learn how to control VGA display from an FPGA chip. The FPGA chip on the DE2-70 board will be programmed as a VGA controller. The controller is responsible for sending the synchronization signals to VGA monitors and the pixel colours as well.

Method

Part1: Generating displays controlled by DE2-70 switches

1. Download from Moodle area a zipped project file, and decompress it within a folder on your H: drive. In the folder, you will see a project called DE2_70_TOP. This project contains the top level module DE2_70_TOP.v, and several reusable cores developed by Altera: a VGA controller core Ctrl.v for synchronization signals. a reset module for resetting the PLL, and an Altera Megawizard components VGA_Audio_PLL.v. Go through the files to gain basic understandings.

2. Modify file DE2-70-TOP.v so that it controls the VGA to display colours according to the settings of the iSWs, especially: Red colour signal is controlled by the [17:12] bits of the switch; Green colour signal is controlled by [11:6] bits of the switch; Blue colour signal is controlled by [5:0] bits of the switch. Note that RGB signals are 10 bits signals here, so you have to decide how to expand the 6 bits read from the switches to 10 bits signals

Part2: Generating display patterns based on current pixel position

1. In this part, you generate a pattern of coloured display. You need to decide what pattern to be generated, but you have to make the pattern taken into account of the current pixel coordinators.

2. The minimum requirement for this part is to generate a pattern which divides the screen into 4 equal areas, with each display a different colour. Use iSW17 to control displaying / not displaying the top-left area, iSW16 for top right area, iSW15 and iSW14 for the two bottom areas respectively.

3. After you achieve the minimum requirement, you will design an animated display pattern. If part of the displayed image moves out of the screen area, you should make it re-appear or moves back. i.e. moving images should not disappear from the screen area indefinitely

Taidot: Verilog / VHDL

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( 1 arvostelu ) manchester, United Kingdom

Projektin tunnus: #4280105

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kamranbabar687

Hi, Please see the PMB.

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ahmedmohamed85

Dear sir, I have more than 5 years experience in fpga programming best regards

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MikroStar

hi, i am an electrical engineer and an embedded system developer. i can help you with this project.

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MicroBrainCenter

Hi, Would be appreciate if you can see your PMB. Regards

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