Project: The project consists of multiple phases. It is to develop a waveform viewer (WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports three analog channels, with a single-level triggering. Only 8 bits of precision will be used for each analog channel. •Phase 1: Develop a minimal system that contains a PC, a UNO board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Only after the FPGA board is awakened, pressing down
a push-button on the FPGA board requests the UNO board to send a character to the PC application which displays the character. You may use Termite as the PC application in this phase, but not in later phases. •Phase 2: Add a data source emulator to the minimal system. When requested by the FPGA board, the microprocessor board sends three channels of data to the PC. Each channel should contain N 8-bit values. (N is a constant to be determined in the lab and the coding should allow N to be changed easily.) The PC application will then graphically display the data. Use artificially generated data that can verify if the PC display works well. •Phase 3: Develop a simple WV system. (1)The FPGA board, once awakened, continuously collects data by using the on-board 3D accelerometer. The data are to be stored in a circular buffer. When the trigger occurs, the FPGA should continue to collect data in the buffer until one-quarter of the samples in the buffer occurred prior to the triggering and three-quarters after the triggering. These samples should then be sent through the UNO board to the PC for display. An LED should also be turned on to indicate that the triggering conditions are met. For the time being, the triggering condition is whether the FPGA push-button is pressed. (2)The UNO board would flash an on-board LED at 0.5 Hz (1 second on and 1 second off) continuously and forward the sequence of data from FPGA to the PC. It stops flashing after the data have been sent to the PC. (3)It may be better to store/send/display one channel of accelerometer data first.
Completed till phase 2 need to do phase 3.
4 freelanceria on tarjonnut keskimäärin 34$ tähän työhön
Programming with FPGA and verilog requires intense hardwork. Even a tiny mistake of code can cause a shorts circuit. I need time to think and reverify everything twice.