Job Description :-
Develop Verification Component of PCIE and other protocol devices including Generators, Transactors, Drivers, Transmiter, Receiver and Transmit and Receive Packet Classes.
Build Simvs, and develop and Run test-cases using these components.
Detailed Requirement :-
1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experience either in RTL Design or TB/Verification.
2) Experience in VLSI - ASIC/FPGA design with following skillset -
a) Verilog, System Verilog,
b) Perl, Bash, Make
c) working in Unix/Linux Environment and Vim/gvim
3) Following are domain expertise -
a) For junor engineers - Intermediate to efficient capability in skillset above. Added advantage is experience in RTL-design and/or verification experience of small to medium sized blocks.
b) For senior engineers that have design exposure - experience in building microarchitecture, developing RTL code/bug fixes for decent size of module.
c) For senior engineers that have verification exposure - experience in building System Verilog based Testbench development experience, building a testplan.
d) Overall exposure to switch, arbitration, ordering, coherency, PCIe etc is added advantage.
4) Soft skills -
a) For junior engineers - interest in learning the design/verification as one of primary interest of freelancing alonside earning money
b) For junior/senior engineers - passion to explore new domains and happy to solve tough problems.
c) For junior/senior engineers - have good energy to finish work in a timely manner, attention to details and humility to learn from right feedback.
5) Time Availibility -
a) Desirable to have at least 10-15+ hours per week for the work.
b) Able to support next 1-2 months minimum.
Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
3 freelanceria on tarjonnut keskimäärin $317 tähän työhön
hi, i have 1 year exprince with verilog,system verilog and UVM. with extensive work with scripting. i can work 10-15+ hours a week and can totally give ou complete support for the duration of project. regards umang