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AXI Stream to MIPI RAW10 and RAW12 Conversion Verilog

Hello,

I want to design a verilog module where input is AXI Stream and output can be either RAW10 or RAW12 pixel data as per input selection. I have my own code for MIPI RAW8. Need to add RAW10 and RAW12 functionality.

Taidot: Verilog / VHDL, FPGA

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Tietoa työnantajasta:
( 0 arvostelua ) Rajkot, India

Projektin tunnus: #26946739

2 freelanceria on tarjonnut keskimäärin 925₹ tähän työhön

yash14191

I have done many projects on functional verification, like AXI protocol verification, APB protocol verification, AHB master and slave UVC verification etc.

₹1250 INR 7 päivässä
(0 arvostelua)
0.0
awe777

Worked on Xilinx FPGAs and AXI modules for a while, and I would like to try on a project-based work.

₹600 INR 10 päivässä
(0 arvostelua)
0.0