We are asked to do the following:
1. Develop a VHDL model of a complete QPSK system, as specified in Section 4.1 in [url removed, login to view], and implement it on a suitable Xilinx or Altera FPGA.
2. Develop and implement a VHDL module and a suitable PC application to send the IQ phase errors to a PC over a USB link and display the errors on the PC screen.
3. Suggest and develop a hardware solution to correcting the IQ phase error and demonstrate your solution in VHDL. In particular, present an analysis of the precision requirements for the data used in within the VHDL code and an analysis for clock speed requirements assuming typical data sampling frequencies.
4. In addition to the technical work specified above, write a chapter in your report on methods, ethics and responsibilities of working in groups towards a common goal. Specifically cover the following issues: group dynamics, shared responsibility, management, risk analysis and treatment of failing elements of the group. A case study should be included as an illustration. The size of the chapter should be approximately 3000-5000 words.
The actual implementation into FPGA is not the most crucial part, but implementation details and simulation (with screen shots and diagrams) is required. Please see attached documents for complete requirements and the report, as it contains all the necessary information. It is also required to document the process in a report form, but the word count can be much smaller, around half of the maximum 15000, concentrating mostly on hardware implementation. Also, point #4 is least important and can be left over in case the time runs out. Matlab code attached should act as basis for VHDL program, as per #1. My absolute deadline is 12 o'clock on Monday afternoon, the 28th of September. Any additional requests, clarifications and negotiations please email to: vaidelizzz[at][url removed, login to view]
Many many thanks
1 freelanceria on tarjonnut keskimäärin 300 $ tähän työhön
I am ready to serve for this request. I have 5+ years of design/verification experience on complex SOC. I have worked on tools like ncsim/specman/Modelsim . the lanh=guages owrked on VHDL/Verilog/'e'/PSL