We have ANTR grammars available for the hardware description languages Verilog and VHDL. These grammars are similar to the ones listed on the [url removed, login to view]\grammars web site, and do not generate AST's.
These grammers do have embedded actions to perform formatting of the output.
In order to implement a variety of features to Verilog and VHDL preprocessors and editors we require AST grammers, tree-walkers and StringTemplates. This project will provide the basic AST structures that will be required to implement these additional features in future projects.
The specific requirements for this initial project are:
1. Convert the existing VHDL and Verilog grammars to support AST's, and strip out the formmatting actions.
2. Build a Tree Grammar for VHDL an Verilog.
3. Incorporate a StringTemplace with the tree grammar that performs adding basic line endings and indentation similar to the existing grammars. Detailed control of line ending, indentation, and other formatting are not required. For this project only a basic formatting capability is required.
Upon request we can provide the Verilog and VHDL grammars, and will answer any questions.