FPGA Validation Framework Mentor

@Fareshassan96

As a seasoned engineer with years of experience in engineering, I have consistently delivered high-quality, research-level solutions across various domains - skills that make me a strong candidate for your FPGA validation framework project. My expertise in Xilinx Vivado, Zynq SoC design, AXI interfaces, and embedded systems will be pivotal in mentoring and guiding your university-level project. With an in-depth understanding of MATLAB/Simulink HDL Workflow Advisor, I can effectively guide the team in designing controller algorithms, generating HDLs, and integrating various IPs. One of my core competencies lies in designing scalable and reusable architectures - a necessity for your project's goal of creating a cohesive framework. Whether it involves building custom Vivado reference designs or devising validation methodologies using known stimulus vectors (which I have hands-on experience with), my aim is to streamline the development process while optimizing functionality. An aspect that undeniably complements this multi-faceted project is my familiarity with arm software interaction and FPGA hardware - an intersection where I have excelled before.

@nichitav7

Hello I can help build this project into a clean, reusable FPGA/SoC validation framework rather than a one-time PID demo. I have hands-on experience with Zynq SoC platforms, AXI-based IP integration, HDL generation flows, embedded firmware interaction, and reusable FPGA architectures for control systems and hardware validation. • I will guide the complete workflow: - MATLAB/Simulink controller modeling - HDL Workflow Advisor configuration - Custom IP packaging - Vivado block design creation - AXI Lite integration - ARM-FPGA communication - Hardware/software co-validation • I can help create a fully custom Vivado reference design instead of relying on autogenerated HDL Workflow Advisor templates, making the framework scalable for future controller IPs beyond PID. • Validation methodology will include: - MATLAB vs FPGA output comparison - stimulus vector testing - synchronized software-driven verification - reusable test infrastructure - captured signal analysis for r[k], y[k], and u[k] • Strong background in: - Zynq SoC & Vivado - AXI interconnects/interfaces - Embedded C on ARM - FPGA verification - reusable IP integration frameworks - controller implementation on FPGA I can also assist in preparing academic-quality documentation and explaining architectural decisions suitable for research submission and presentation. Regards, Nichita.