FPGA Real-Time Sobel Detection

₹600-1500 INR

Käynnissä

Julkaistu 4 päivää sitten

₹600-1500 INR

Maksettu toimituksen yhteydessä

I am building a Verilog-based, real-time Sobel edge detector that streams video from an OV7670 camera to a monitor over VGA on a Nexys A7-100T board, all within Xilinx Vivado. The architectural concept is clear, yet the project’s success now depends on rigorous simulation, validation, and concise documentation suitable for an academic submission. Your main focus will be designing an efficient test and simulation strategy: self-checking test-benches, frame-level functional coverage, timing verification, and any other diagnostics that prove the design meets real-time performance. I am open to whichever simulation environment you consider best—whether you stay inside Vivado’s integrated simulator or introduce ModelSim, Verilator, or another workflow—provided it integrates smoothly with the existing Vivado toolchain. Please send a detailed project proposal that outlines: • your step-by-step verification methodology • key milestones and expected artefacts • any reusable IP or frameworks you plan to leverage Expected deliverables: • Parameterisable Verilog modules for camera capture, Sobel operator, line buffering, and VGA output • Comprehensive, automated test-benches with clear pass/fail criteria • Simulation logs and performance reports demonstrating real-time throughput on 640×480 @30 fps (or higher if feasible) • A Vivado project and bitstream ready to load onto the Nexys A7-100T • A brief design document (2-3 pages) explaining implementation choices, resource utilisation, and how results were measured The project is time-sensitive but manageable; clear proposals that map effort to milestones will help us start quickly and finish confidently.

Electrical Engineering

Electronics

Projektin tunnus (ID): 40274949

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Aktiivinen 4 päivää sitten

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Myönnetty käyttäjälle:

@Mostafaihab1

Hi Client, As a Digital IC Design Engineer specializing in RTL design and FPGA prototyping, my focus is on delivering hardware that works flawlessly on the board, not just in simulation. I know exactly what a high-quality academic submission demands. To guarantee pixel-perfect accuracy, my verification strategy relies on a 'golden model' approach. I use Python scripts to process raw images, then compare those results pixel-by-pixel against the RTL simulation in a self-checking testbench using QuestaSim, and I will also double-check the integration in Vivado. Our key milestones will start with delivering the core Sobel and line-buffer modules, followed by automated simulation logs and final timing closure. This ensures the architecture remains efficient and entirely stable at 640×480 @ 30 fps, resulting in a fully 'plug-and-play' bitstream ready for your Nexys A7-100T.

₹4 000 INR 8 päivässä

5,0

(1 arvostelu)

1,0

2 freelancerit tarjoavat keskimäärin ₹2 300 INR tätä projektia

@InjectAI

Hi, I fully understand your requirements and can provide Verilog development support with strong skills in FPGA design, video processing, and Xilinx Vivado. I am based in Pakistan and have hands-on experience building real-time hardware accelerators, camera interfacing, and VGA controllers for FPGAs. .................. What I will Deliver .................. Parameterisable Verilog modules for camera capture, Sobel operator, line buffering, and VGA output Comprehensive, automated testbenches with clear pass/fail criteria Simulation logs and performance reports demonstrating real-time throughput on 640×480 @30fps A complete Vivado project and bitstream ready for Nexys A7-100T A concise design document (2-3 pages) explaining implementation choices and resource utilisation .................. Tech Stack use for this Project .................. Verilog / SystemVerilog for RTL design Xilinx Vivado simulator for synthesis and implementation OV7670 camera interface protocol VGA timing controller for 640×480 @60Hz output Block RAM for line buffering Xilinx ILA cores for on-chip debugging Verification Methodology includes module-level self-checking testbenches, frame-level integration testing, timing analysis, and hardware validation. I offer competitive rates and can ensure a thoroughly validated, academic-ready solution. You can review my portfolio and similar FPGA projects on my profile. Regards,

₹600 INR 7 päivässä