FPGA implementation of music algorithm for direction of arrival of signal.

₹3000-7000 INR

Käynnissä

Julkaistu 12 päivää sitten

₹3000-7000 INR

Maksettu toimituksen yhteydessä

I need a synthesizable, timing-clean Verilog implementation of the classic MUSIC (Multiple Signal Classification) algorithm that can estimate the direction of arrival of one or more narrow-band signals received on a uniform linear array of four antennas. The end use is a radar front-end, so accuracy takes priority over latency or power. Scope • Design the fixed-point signal-processing chain on an FPGA (I am currently working with Xilinx Series parts; feel free to suggest an equivalent if it helps meet timing). • Implement covariance matrix formation, eigen decomposition and the pseudospectrum peak search entirely in hardware; no soft-core processors or external DSP chips. • Include provisions for array calibration coefficients so the design can be tuned on-site. To help integration, please structure the RTL into clearly documented, reusable modules and accompany them with a self-checking testbench that compares hardware output against a golden MATLAB/Python reference. Simulations should run in Xilinx Vivado. Provide me the output video on fgpa and all codes so that i can implement on my pc also Deliverables • Synthesizable Verilog source and hierarchy file • Comprehensive testbench and reference script • Simulation waveforms demonstrating correct angle estimation for at least two simultaneous emitters at different SNR levels • Resource, clock-rate and accuracy report from post-implementation timing analysis Acceptance criteria 1. Angle estimation error ≤ 1° RMS across −60 dB to 0 dB SNR in the test set 2. Post-route clock speed ≥ 100 MHz on a Xilinx Artix-7 (or mutually agreed equivalent) 3. All code passes lint (Verible or similar) and has >90 % branch coverage in the testbench Once the core meets these targets we can discuss optional enhancements such as adaptive beamforming or latency optimisation, but the focus for this milestone is rock-solid accuracy for radar trials.

FPGA

Signal Processing

Digital Signal Processing

Simulation

Matlab and Mathematica

Electrical Engineering

LabVIEW

Verilog / VHDL

Projektin tunnus (ID): 40251663

Tietoa projektista

7 ehdotukset

Etäprojekti

Aktiivinen 11 päivää sitten

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Freelancerin tarjouskilpailun edut

Aseta budjettisi ja aikataulu

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Myönnetty käyttäjälle:

@Mostafaihab1

Hi Client, I’m a Digital IC Design Engineer specializing in Verilog/SystemVerilog and Xilinx FPGA design. I’ve built complex, timing-clean RTL systems from scratch, including pipelined processor architectures, and I’m experienced with fixed-point design, modular RTL structure, and Vivado timing closure. I can implement the full hardware-based MUSIC pipeline (covariance matrix, eigen decomposition, pseudospectrum search) in synthesizable Verilog, fully timing-clean for Artix-7 or any at ≥100 MHz. I’ll provide clean, reusable RTL, a self-checking Vivado testbench with MATLAB/Python reference comparison, simulation waveforms, and post-route timing/resource reports.

₹4 000 INR 7 päivässä

5,0

(1 arvostelu)

1,0

7 freelancerit tarjoavat keskimäärin ₹25 571 INR tätä projektia

@nabeelraza1993

MUSIC on FPGA only works when the fixed point math is planned carefully from covariance to peak search. Well, what I can do for you as an electronics engineer is design a synthesizable Verilog implementation of the MUSIC pipeline for a 4 antenna ULA, with modular RTL for covariance formation, eigen decomposition, pseudospectrum evaluation, and peak detection, plus calibration coefficient support for field tuning. In fact, I designed a high power 10000 watt LED dimmer for a UK client and I also built an 8 bit SAR ADC logic in Cadence, so I am comfortable with timing clean digital design, fixed point logic, and FPGA ready verification workflows.

₹3 000 INR 7 päivässä

4,9

(43 arvostelut)

5,2

@divyam12345

Dear Sir/Madam, I have solid experience in FPGA design, especially in signal processing tasks like radar and communications. I'm confident I can deliver a precise and efficient Verilog implementation of the MUSIC algorithm tailored to your radar system. With expertise in Xilinx FPGAs and hardware algorithms, I can ensure high performance and accuracy. Let’s connect in the chatbox to discuss the project further, including the budget and timeline. To know more about my experience, let's talk in a freelancer call, and I can share more details and sample works in the chatbox. I am ready to work with you, please connect in the chatbox for further discussions. Thank You. Dr. Divya.

₹7 000 INR 7 päivässä

5,0

(9 arvostelut)

3,5

@Fareshassan96

Drawing from my expertise in Electrical Engineering and Simulation, specifically in the field of FPGA implementation, I am confident in my ability to deliver the FPGA design you require for your project. Having worked extensively with Xilinx Series parts like the Artix-7, I am well-acquainted with the tools and techniques needed to produce a clean, timing-driven Verilog implementation. My proficiency in creating hardware-centric designs with no reliance on soft-core processors or external chips aligns perfectly with your expectations. Additionally, my great attention to detail and commitment to problem-solving will ensure that your FPGA design not only meets but exceeds your demands. I'll provide you with thorough documentation and reusable modules that streamline further integration, as well as precisely crafted calibration coefficients for easy on-site adaptation. Furthermore, I'm confident in implementing a reference testbench that will give you accurate insights into design performance by comparing hardware output against a golden reference. Lastly, not only will I test your implementation against RMS performance targets across varying SNR levels but also generate post-implementation timing analysis, simulation waveforms and clock speed reports using Veribile or similar linting tool to exceed your acceptance criteria.

₹30 000 INR 7 päivässä

4,9

(6 arvostelut)

3,7

@QuantCore

With a PhD in VLSI and 15 years of experience specializing in FPGA-based signal processing, I am uniquely qualified to deliver a high-fidelity MUSIC implementation. My approach bypasses soft-cores to ensure true real-time performance. I will implement a custom hardware pipeline featuring a fixed-point . To meet your 100MHz timing on Artix-7, I utilize deeply pipelined CORDIC engines for the pseudospectrum peak search, ensuring the design is both synthesizable and timing-clean. ### My Proposed Workflow: * **Gold Reference:** I’ll provide a bit-accurate MATLAB model to validate the fixed-point word growth. * **RTL Architecture:** Modular Verilog with integrated calibration registers for site-tuning. * **Verification:** A self-checking UVM-lite testbench achieving >90% branch coverage. I have extensive experience integrating Matlab/Simulink with Vivado System Generator and HDL Coder, ensuring the "golden" reference matches the hardware output perfectly.

₹5 000 INR 7 päivässä

0,0

(0 arvostelut)

0,0

@igor13th

I’m interested in implementing a fully synthesizable, fixed-point Verilog (I would even suggest systemverilog) version of the MUSIC algorithm for a 4-element ULA targeting Xilinx Artix-7(usually use these ones to implement DSP). However, the proposed budget (5000 INR) and 7-day timeline are not realistic for a hardware-only eigen decomposition and pseudospectrum implementation meeting: <=1° RMS error down to −60 dB SNR >=100 MHz post-route timing Full lint compliance and >90% coverage Self-checking testbench against verification language reference This project requires careful fixed-point modeling, matrix conditioning analysis, hardware-efficient eigen decomposition (Jacobi/QR/CORDIC-based), and timing closure validation

₹125 000 INR 40 päivässä