VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation.
Verilog files and simple testbench to prove the design.
10 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_26% %project_currencyDetails_sign_sub_27% tähän työhön
Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 5 years. Please let me know if the requirement is still there we can work together. Thanks.
Hello sir, i am girish Phalake, FPGA design engineer with better industry experience, i am very good at paper design and also good in english Thank you!