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Build me a UVM oroject

Myönnetty käyttäjälle:

digvijay1108

Verification Engineer here having 3.5 years experience in developing UVM test benches. Relevant Skills and Experience System verilog,UVM,perl,python,make file

$133 USD 5 päivässä
(0 Arvostelua)
0.0

6 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_26% %project_currencyDetails_sign_sub_27% tähän työhön

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using system verilog please check my profile also please message me

$250 USD 1 päivässä
(382 arvostelua)
7.8
loi09dt1

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise Lisää

$155 USD 5 päivässä
(165 arvostelua)
6.8
vlsirajagopal

Having very good experience in UVM based verification methodology. Using systemverilog UVM for more than 7 yrs. I can do this well without any issues.

$277 USD 3 päivässä
(16 arvostelua)
5.1
Trendesque

Sir, Trendesque is a custom software services firm based in Lahore, Pakistan. We are a team dedicated to Embedded designs, PCB designs, Wireless communication, Circuit designing, Automation, Arduino, Raspberry pi, Ver Lisää

$500 USD 10 päivässä
(0 arvostelua)
0.0
vpakwong

I have 5+ years in UVM and systemverilog. I worked at Intel and currently develop UVM test bench and environment. please message me privately if my service can be of use.

$666 USD 5 päivässä
(0 arvostelua)
0.0