system verilog, uvm
9 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_26% %project_currencyDetails_sign_sub_27% tähän työhön
Hi, Can you share more details about your project? I have done similar project and understood the project outline. Please give me a chance. A trial will convince you. Looking forward to work with you.
I am a qualified design and verification engineer who work on this at industry level. I have more than 4 years+ knowledge in verilog, system verilog and UVM.
I am Currently working on ASIC Verification project in reputed product company, using my skill sets UVM, System Verilog. Previously I had an experience on Verilog for digital design and Verification.