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Median filter using Xlinx

4 freelanceria on tarjonnut keskimäärin ₹2695 tähän työhön

IslamAdam998

Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and othe Lisää

₹5000 INR 7 päivässä
(11 arvostelua)
3.8
vinendra77

Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and FSM and had a working Lisää

₹1500 INR 2 päivässä
(9 arvostelua)
2.9
Livebinary

please let me know if you are interested in my bid. please ping me if you are interested in my bid please let me know if you are interested in my bid.

₹2778 INR 1 päivässä
(0 arvostelua)
0.0
rafean

Hello, I can help you, I have experience with video design for FPGA devices, let me know more about your needs.

₹1500 INR 7 päivässä
(0 arvostelua)
0.0