I need help with simulation using LTSpice to characterize performance of a few SRAM bitcell.
I need to collect data on a few different SRAM bitcell topology (namely, 6T, 7T, 8T design). Will be looking into their Static Noise Margin (SNM), power leakage, read and write margin.
I also need a 4x4 array to be built on the SRAM bitcell being characterized, and analyse the power leakage of that array.
Will be using transistor device model from Predictive Technology Model (PTM) in 45nm LP.
Hello. I will help you to complete this project. You can check my profile and notice that I am skillful enough for this project. Wish further discussion via chat. Thanks.
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I am an electrical engineer and interested in your project. I have read the description of your project. Kindly send me text to discuss the project in details. Thanks