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Verilog Project - E123 Mux/E1 Framer

E123 Mux:

The E123MUX is a system that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T [url removed, login to view] Recommendation. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. Any 4 lines of 16 E1s can be multiplexed to one [url removed, login to view] E123MUX uses memory locations for setting control bits.

Problem Statement: Part A

In this part of the assignment, the delegate needs to identify the E12MUX architecture and model the E12MUX in Verilog. The FPGA being targeted should be considered and synthesizable code should be written targeting the efficient usage of chosen FPGA resources. The model should be simulated in any industry standard simulator

Perform the following and report the same in your assignment:

1. Identify the sub blocks for the selected architecture of E12MUX

2. Model the design using verilog HDL, carry out the functional simulation and verify the results

with appropriate input test cases.

3. Simulation and analysis of results obtained using multiple test cases to prove E12MUX

Problem Statement: Part B

1.) For the E12MUX designed in part A above write an efficient test bench in Verilog

2.) The test bench should completely cover the whole design

3.) Use the concept of File I/Os to make the test procedure more efficient

4.) Synthesize the designed E12 MUX in an appropriate FPGA development board

5.) Identify appropriate synthesis constraints for mapping the design efficiently on the board

6.) A demonstration should be given to the module leader answering principles of E12MUX.

Now I do have the VHDL code for the E1 framer/deframer available with me, and all I need is for some one to convert it to verilog and verify that its synthesizable and meets the above mentioned criteria.

I'm on Yahoo.

I only need the verilog code and the explanation about the blocks and the functionality(how the code is working), I do not need any detailed reports,thesis etc.

I would need this assignment strictly by 27th Sept. 09. I'm navz_aqua007

Please let me know if you'll be able to help me with that and also how much will be the cost.

Taidot: elektroniikka, Mikrocontroller, Verilog / VHDL

Näytä lisää: fpga mux project, e123 mux, framer verilog, verilog framer, framer vhdl, verilog code framer, framer vhdl code, e123 mux vhdl, vhdl code framer, framer verilog code, e123 mux vhdl project, verilog project, framer using verilog, e123 mux code, e123 mux vhdl code, simulation framer vhdl, mux board, test bench code verilog framer, multiplexer vhdl, framer design fpga, design framer vhdl verilog, mux verilog, e123mux, project verilog, verilog code

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9 freelanceria on tarjonnut keskimäärin 256 $ tähän työhön

makjee

lets talk details on pmb

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contact2web

Please see PMB

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ssirota

I'm a expert VHDL programmer. If it's ok for you. I can do it. My BID it's superior to your limit because the limit time it's a must. Regards

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dhavalmalaviya

Please have a look at my PM.

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STDC

Bidder Comments : Dear Sir, Kindly refer to your PM for more details. Thanks & Regards, SANDS Team.

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rutawari

Hello, I am an expert Verilig and VHDL programmer. I have extensive experience in Design/Verification. I can finish this withing the reqd. time.

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fahadislam2002

I would be working with working in ISE version7 or 8 using spartan fpga. Simulator will be modelsim. I am very much experienced with both VHDL and verilog (also system c). Bid is negociable as its my first freelance Lisää

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satishsub

I have ten years of experience in telecommunication RTL design from architecture and PAR using xilinx. I have worked on Ethernet, Wireless projects, SONET/SDH. Please have a look at my profile in linkedin : linkedin.c Lisää

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fathahrahman

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