I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.
If you want to bid on this project, please read the entire description and let me know your experience with logic development.
10 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_18% %project_currencyDetails_sign_sub_19%/tunti tähän työhön
I have more than 8 yrs of exprience in HDL(verilog,Systemverilog,VHDL) implementation and RTL developement and asic verification as well. I can do this very well.
hello I am fpga expert having 5 years of industry experience on developing complex dsp and communication systems using fpgas. I offer a fixed price of 50 dollars for this project and I will finish it in 7 days. thanks.