The serdes circuit should take 16 16-bit data from one memory and transfer it to another memory serially.
The design will have 2 parts.
Following should be the functionality:
Data from a preset memory (16 locations of 8-bits each) is converted to a serial stream of data and sent out of the FPGA chip through a single pin...
...The serial transmission from part 1 is captured and converted to parallel data before being stored in another memory location( as 16 locations of 8-bits).
The data in this memory should match with the data in memory in Part 1.
Both parts are to be implemented in the same FPGA ....The serial out from part 1 will be physically connected with a wire to the serial input in part 2 (in a loopback configuration)
This circuit should display the contents of memory in part 2 on seven segment displays.( two seven segment)
A pushbutton should be used to single step through all the memory locations...remember the contents displayed should match what was preset in the memory in part 1
22 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_26% %project_currencyDetails_sign_sub_27% tähän työhön
Dear sir I have more than 10 years experience in digital design using FPGA please check my profile also please message me so that we can discuss Best regards
hello i am an electronics engineer having 5 years of experience on fpga design. I designed 4 gigabit serdes in virtex 7 fpgas. I can do it easily in 2 days. thanks. price is negotiatable.
Hello, I have expertise in FPGA Design and Verification. I would like to work in this project. Would you like me to deliver the code in Verilog or VHDL? Please get back to discuss further. Thanks Kartik
Hi, As a FPGA engineer, I am working on spartan-6 development kit in xilinx family, can build VHDL design within a few days. Thanks, Cheng Jiang.