1. Develop Verilog modules for the following logic circuits.

a) XOR gate with inputs A, B and output Z.

(10 points)

b) 2 to 1 Multiplexer (A,B as the data inputs and S as the select input and F as the output )

(10 points)

Implement testbenches to analyze the design and run the behavioral simulation using Xilinx ISim.

Submit printouts of the timing diagrams obtained during simulation together with the Verilog codes.

Indicate the output transitions with respect to the inputs on the printout.

Taidot: Verilog / VHDL

Näytä lisää: circuits design, xor, xilinx, microprocessor 2, behavioral, design gate, verilog design, microprocessor design, multiplexer, design implement editor, logic gate, microprocessor project using pic

About the Employer:
( 30 reviews ) BEAVERCREEK, United States

Projektin tunnus: #4226999

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hi i can get this done.Professional verilog designer is here

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I am interested. Please share details.

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I am a young male Ugandan who highly cherishes hard work, excellence and integrity and always striving to find a challenging position to meet my competence, skills, education and experience

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