1. Develop Verilog modules for the following logic circuits.
a) XOR gate with inputs A, B and output Z.
b) 2 to 1 Multiplexer (A,B as the data inputs and S as the select input and F as the output )
Implement testbenches to analyze the design and run the behavioral simulation using Xilinx ISim.
Submit printouts of the timing diagrams obtained during simulation together with the Verilog codes.
Indicate the output transitions with respect to the inputs on the printout.
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