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SMC Interface and SPI Slave Logic for CPLD Project

1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N)

2) Implement SPI Mode-0 SPI Slave in CPLD logic

3) Implement Dual SPI Slave mode in CPLD logic

4) Implement QUAD SPI Slave mode in CPLD logic

5) Implement general purpose I/O (8-bit) Port B in CPLD logic

6) Implement JTAG Host shift logic in CPLD logic

Taidot: C-ohjelmointi, elektroniikka, FPGA, Mikrocontroller, Verilog / VHDL

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Tietoa työnantajasta:
( 2 arvostelua ) Redmond, United States

Projektin tunnus: #15694402

5 freelanceria on tarjonnut keskimäärin %project_bid_stats_avg_sub_18% %project_currencyDetails_sign_sub_19%/tunti tähän työhön

ahmedmohamed85

A proposal has not yet been provided

$33 USD / tunti
(360 arvostelua)
7.7
$55 USD / tunti
(74 arvostelua)
7.0
Dyumnin

Dear Sir/Madam, I, on behalf of Dyumnin Technologies am submitting this proposal in response to your project for SMC Interface and SPI Slave Logic for CPLD Project. Dyumnin Technologies was founded in 2016 by a Lisää

$27 USD / tunti
(3 arvostelua)
4.1
jenistenalbert

I have very good experience in SPI implementation in CPLDs which will let me finish your project on time

$22 USD / tunti
(0 arvostelua)
0.0
$22 USD / tunti
(0 arvostelua)
0.0