After reading over your project this looks like a perfect fit for my skill sets.
I have 10+ years of FPGA design and Verilog/VHDL experience.
While I’m certain there will be others who underbid me on thisLisää
I am an RTL Design Engineer, specializing in ASIC and FPGA design.
I have used tools like sdAccel by Xilinx and have done projects with openCL to netlist as well.
I will spend a day or two to understand theLisää
I tried to convert AES algorithm into FPGA platforms.
Also I am very familiar with FPGA.
I am now working as an FPGA prototyping engineer in an ASIC company.
I am very interested in the project you posted.
If it isLisää
I am a professional LabVIEW developer and a FPGA Engineer.I have worked across FPGA, be it Xilinx or NI FPGA and I have professional experience in Verilog,VHDL and LabVIEW.I have worked in platforms like ModelSIM, XiliLisää
I'm an experienced hardware developer in the Silicon Valley bay area, CA working on security algorithms implementation in ASICs. I have extensive experience writing HDL code and making sure it is synthesize can meets tLisää