I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.
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hello Myself Akriti electronics and communication engineering Student at NIT Jalandhar with 6 month experience in VHDL and system designing. But i am comfortable with VHDL using xilinx not verilog.