ASIC Design Verification Specialist

@mayankinnovative

Hi, As per my understanding: You require verification support covering directed/random test development, UVM-based environments, coverage closure, and deep RTL/firmware debug, ideally with DDR or memory controller exposure. Implementation approach: Develop scalable UVM testbench and sequences Drive functional/code coverage and assertions Debug failures via simulation, waveform, and log analysis Is the environment UVM-based already? Target simulator (VCS/Questa/Xcelium)? Current coverage status? I will share my portfolio on your first message. Confident we can align after our first discussion.

@vishal1145

Your DDR controller verification will fail at corner cases if you're not modeling protocol violations and power state transitions correctly. Most teams catch these bugs in silicon, which costs 6 months and $2M in respins. Before architecting the testbench, I need clarity on two things: What's your current functional coverage target - are you aiming for 95% or full closure? And are you verifying LPDDR4/5 or DDR4/5 protocols, because the power management sequences are completely different? Here's the verification strategy: - SYSTEMVERILOG + UVM: Build a constrained-random testbench with protocol checkers that catch command timing violations, refresh conflicts, and ZQ calibration edge cases that directed tests miss. - PYTHON + PERL: Automate regression flows with coverage tracking and failure triage scripts that parse waveforms to identify if bugs are RTL, testbench, or firmware-related. - DDR PROTOCOL VERIFICATION: Implement read/write leveling scenarios, bank interleaving stress tests, and thermal throttling sequences that expose PHY interface timing issues before tapeout. - CODE COVERAGE ANALYSIS: Set up toggle, branch, and FSM coverage to identify untested logic, then generate targeted tests to close gaps without writing redundant scenarios. I've closed verification on 4 memory controller designs including LPDDR5 PHY integration where we caught a critical DLL lock failure that only triggered during temperature transitions. I don't start building tests until we align on the coverage plan and known silicon errata from previous generations. Let's schedule a 20-minute technical call to review your RTL architecture and define the verification closure criteria.

@murtuza90

As a probe verification engineer who has been simulating and verifying complex ASIC designs for over 6 years, I am confident in my ability to excel in this role. One of my biggest strengths lies in my competency with C/C++ and hardware description languages like Verilog, System Verilog which are integral for designing and debugging verification tests. Alongside that, my understanding of DRAM or Memory Controller verification acts as an added bonus since it maps perfectly with your Preferred Experience requirements. In addition to these technical skills, my collaborative spirit sets me apart. Throughout my career, I've worked side by side with architects, hardware engineers, and firmware experts to ensure smooth project execution. Understanding new features and successfully resolving design defects all underline my ability to adapt and deliver. Lastly, I am a polyglot when it comes to scripting languages; proficient in Python, Perl and TCL. This versatility allows me to not only write powerful yet scalable code but also exploit the power of simulation tools to efficiently debug both the firmware and RTL code. Your project description almost dances with my skillset - it's like you write down all the things I focused upon during my academic journey Selecting me ensures that not only will your tests be develop precisely but you'll have access to a multifaceted problem solver at every step of your project. Let's get ready to tackle the next challenge!

@Hemantt841

Thank you for considering my proposal for the ASIC Design Verification Specialist project. I was immediately drawn to the detailed responsibilities outlined in the project description, particularly the focus on developing/maintaining tests for functional verification and providing technical support to other teams. With over 7 years of experience in software development, I have successfully completed numerous projects similar to this one. One project that stands out is when I developed verification tests for a complex ASIC design, collaborating closely with RTL and firmware engineers to ensure a seamless verification process and timely detection of design defects. My approach to completing this project would involve: - Creating directed and random verification tests using Verilog, System Verilog, and UVM - Utilizing scripting languages like Python for test automation - Collaborating with cross-functional teams to understand new features for verification - Implementing Design for Test methodologies for comprehensive verification coverage - Debugging firmware and RTL code using simulation tools efficiently I have extensive experience with C/C++, Verilog, System Verilog, UVM, and scripting languages like Python, which align perfectly with the project requirements. Additionally, my background in DDR and Memory Controller verification further strengthens my capability to deliver h

@ssldevmaster

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