Xilinx project työt

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    608 xilinx project työtä löytyi, hinnoittelu EUR

    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

    €2823 (Avg Bid)
    €2823 Keskimäär. tarjous
    7 tarjoukset
    Digital To Analoge 6 päivää left

    ...to run Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation can be done in Tina software. An explanation of the VHDL code to be supplied so

    €88 (Avg Bid)
    €88 Keskimäär. tarjous
    2 tarjoukset

    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

    €39 (Avg Bid)
    €39 Keskimäär. tarjous
    4 tarjoukset
    Update Miner for FPGA 4 päivää left

    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

    €549 (Avg Bid)
    €549 Keskimäär. tarjous
    9 tarjoukset

    We are looking for one freelancer to develop FPGA software for best mining algo using Xilinx FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be perfectly optimized.

    €3967 (Avg Bid)
    €3967 Keskimäär. tarjous
    11 tarjoukset

    In the Input section the database(Collection of Email like 10,000 mails), Pre-filter and classifier( based on the Naive Baye's algorithm) link attached at the bottom. In Output section, it should be a Spam mail and Non-Spam mail. 1) Use of Dynamically modifying database to store the previously checked Emails and program to append currently scanning Emails. 2) Percentage of Spam. 3) Efficienc...

    €222 (Avg Bid)
    €222 Keskimäär. tarjous
    8 tarjoukset

    The goal is to design a game on Xilinx FPGA. More details on chat. The deadline will be 3 days. Only serious bidders who can complete in 3 days should bid. No Excuses. Time wasters avoid bidding, please.

    €105 (Avg Bid)
    €105 Keskimäär. tarjous
    3 tarjoukset
    SERDES RTL DESIGN Loppunut left

    ...be connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible with the GTH Transceiver. Your tasks are 1. Write the PCS RTL code 2. Provide a compatible

    €48 / hr (Avg Bid)
    €48 / hr Keskimäär. tarjous
    13 tarjoukset

    ...programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is urgent. Entire work to be completed in 2 - 3 weeks. Any freelancer with experience in integrating system level codes in VHDL, basics of digital signal processing and programming Xilinx Virtex-6 FPGA

    €756 (Avg Bid)
    Paikallinen
    €756 Keskimäär. tarjous
    11 tarjoukset
    €9 / hr Keskimäär. tarjous
    1 tarjoukset

    Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

    €117 (Avg Bid)
    €117 Keskimäär. tarjous
    9 tarjoukset

    Please refer the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    €38 (Avg Bid)
    €38 Keskimäär. tarjous
    13 tarjoukset

    ...with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL

    €152 (Avg Bid)
    €152 Keskimäär. tarjous
    12 tarjoukset

    ...with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL

    €130 (Avg Bid)
    €130 Keskimäär. tarjous
    4 tarjoukset

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €359 (Avg Bid)
    €359 Keskimäär. tarjous
    2 tarjoukset

    I am looking for Xilinx SDx OpenCL expert, who can convert github miner project into FPGA hex file in Xilinx SDx. Don't bid if you do not have experience.

    €4371 (Avg Bid)
    €4371 Keskimäär. tarjous
    8 tarjoukset

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €133 (Avg Bid)
    €133 Keskimäär. tarjous
    7 tarjoukset

    I need help with the structural in Xilinx. I will give you full details. Regards

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    23 tarjoukset

    1. Configure 4 UARTs (Rx Only). 2. Configure 2 SPI Slaves. 3. Data coming on UARTs are split into two groups. a. 2 UARTs first SPI slave and another 2 UART data Second SPI slave. 4. Data pattern on UART will be "Magicnumber(4 bytes), Length (4 bytes), Payload".

    €246 (Avg Bid)
    €246 Keskimäär. tarjous
    2 tarjoukset

    ...Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible light communication

    €3884 (Avg Bid)
    €3884 Keskimäär. tarjous
    27 tarjoukset

    Setting up Xilinx ZCU102 board for Petalinux flow, using on-board DDR, functions include HDMI input, HDMI output, and customer provided IP interface. Also looking for firmware development tool chain setup.

    €49 / hr (Avg Bid)
    €49 / hr Keskimäär. tarjous
    9 tarjoukset

    ...The system includes an FPGA part. We use Xilinx Vivado as our development platform and Xilinx all programmable SoC as our hardware platform. The project involves transmitter and receiver design. We have implemented 4-PAM (pulse amplitude modulation) and one feature to remove the unwanted interference. The project is not complete and requires troubleshooting

    €4011 (Avg Bid)
    €4011 Keskimäär. tarjous
    25 tarjoukset

    build a communication block in VHDL at Xilinx environment

    €352 (Avg Bid)
    €352 Keskimäär. tarjous
    14 tarjoukset

    Implement Communication VHDL Comm port on Xilinx FPGA part

    €110 (Avg Bid)
    €110 Keskimäär. tarjous
    16 tarjoukset

    I already have a working C code which works on Zynq PS. I need to get it working over PL.

    €123 (Avg Bid)
    €123 Keskimäär. tarjous
    10 tarjoukset
    Task in VHDL Loppunut left

    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

    €101 (Avg Bid)
    €101 Keskimäär. tarjous
    19 tarjoukset

    Hi Okamoto T., I noticed your profile and have a few questions. Are you equipt to do PCB design of a PCI-E card that has a Xilinx Artix 7?

    €18 / hr (Avg Bid)
    €18 / hr Keskimäär. tarjous
    1 tarjoukset

    The firmware will need to have base functions for interfacing the Bluetooth...firmware will need to have base functions for interfacing the Bluetooth radio and other communication (i.e. UART, SD Card, Ethernet, etc. ) and loading the memory. Using Xilinx, VIVADO software. and also PicoZed 7010 SOM + FMC Carrier V2 (xc7z010clg400-1) processing system

    €138 (Avg Bid)
    €138 Keskimäär. tarjous
    5 tarjoukset

    I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.

    €14839 (Avg Bid)
    €14839 Keskimäär. tarjous
    11 tarjoukset

    The integration of CPRI IP integration into LTE RRH System.

    €591 (Avg Bid)
    €591 Keskimäär. tarjous
    5 tarjoukset
    xilinx project Loppunut left

    design a stat has two output and one input

    €60 (Avg Bid)
    €60 Keskimäär. tarjous
    13 tarjoukset

    We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.

    €8066 (Avg Bid)
    €8066 Keskimäär. tarjous
    11 tarjoukset

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    €88 (Avg Bid)
    €88 Keskimäär. tarjous
    8 tarjoukset

    I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory

    €321 (Avg Bid)
    €321 Keskimäär. tarjous
    9 tarjoukset

    i will explain in brief when we discuss

    €14 / hr (Avg Bid)
    €14 / hr Keskimäär. tarjous
    12 tarjoukset

    Hi, I want to implement a CNN in a Xilinx FPGA using Caffe or Tensorflow.

    €216 (Avg Bid)
    €216 Keskimäär. tarjous
    2 tarjoukset

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    €75 (Avg Bid)
    €75 Keskimäär. tarjous
    5 tarjoukset
    fpga programming Loppunut left

    We are looking for a FPGA programmer, to build a mining software for Xilinx Virtex UltraScale+ FPGA VCU1525.

    €8185 (Avg Bid)
    €8185 Keskimäär. tarjous
    13 tarjoukset

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [kirjaudu nähdäksesi URL:n] Using PG236 [kirjaudu nähdäksesi URL:n]

    €112 (Avg Bid)
    €112 Keskimäär. tarjous
    3 tarjoukset

    "Need FPGA implementation of a Radar Matched Filter using Xilinx FPGA "

    €67 (Avg Bid)
    €67 Keskimäär. tarjous
    4 tarjoukset

    ...pictures. We need a Zynq developer to write FPGA code that will process the pictures. We're using the Zynq 7010 clg225: [kirjaudu nähdäksesi URL:n] Specifically, we want streaming FPGA code that will: 1. Subtract the median-filtered image from the original image (i.e. output = image

    €505 (Avg Bid)
    €505 Keskimäär. tarjous
    2 tarjoukset

    Hi Chris, I saw a message stating you had experience creating a FPGA miner. I am trying to learn how to program FPGA and wanted to start w...crypto miner so I can try to pay off the hardware. I am willing to pay to get some assistance and pointers and any example projects you are willing to share. My hardware is Xilinx AVNET VCU-1525 development kit.

    €31 - €31 / hr
    €31 - €31 / hr
    0 tarjoukset

    BId only if u can do only the second Part for $50 an...seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part

    €155 (Avg Bid)
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    FPGA programming Loppunut left

    We are looking for one freelancer to develop FPGA software for Cryptonight mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be

    €4297 (Avg Bid)
    Mainostettu
    €4297 Keskimäär. tarjous
    10 tarjoukset

    ...output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No other work is needed at this point. I will provide a Xilinx Spartan III demo board made by Digilent ([kirjaudu nähdäksesi URL:n]), if necessary and have it shipped to the developer. The developer

    €95 (Avg Bid)
    €95 Keskimäär. tarjous
    10 tarjoukset

    Hi, there I am looking for an experienced FPGA developer that can implement HASH algorithm on FPGA. We can discuss in details via chatting. Please contact me! I am waiting for someone now. Welp,

    €2101 (Avg Bid)
    €2101 Keskimäär. tarjous
    5 tarjoukset

    - PCI transmition logic implement with ZC102 board and Xilinx PCI Solution v1.3 - windows device - sample wndows program

    €1143 (Avg Bid)
    €1143 Keskimäär. tarjous
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    fpga soft radio Loppunut left

    Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client

    €334 (Avg Bid)
    €334 Keskimäär. tarjous
    4 tarjoukset

    Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. I already have a complete project written in vhdl including other modules apart of this project. I need you to simulate and fix the data transmission part between the client application to the DAC AD9764, which is

    €174 (Avg Bid)
    €174 Keskimäär. tarjous
    8 tarjoukset

    ...denke so im rahmen von 20-40h im mai. ich benoetige einen DMA test, also die maximale transfergeschwindigkeit von einem PDM pin (input) bis in den linux userspace. HW und xilinx build-server sind vorhanden. ich habe das board (z-turn myr) bis jetzt noch nicht getestet. das input sollte als vivado AXI4lite IP auf der GP clock (100MHz) rund um die 400

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