Vhdl verilog fpga työt

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    5,804 vhdl verilog fpga työtä löytyi, hinnoittelu EUR
    Simple VHDL task Loppunut left

    Simple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL task

    €76 (Avg Bid)
    €76 Keskimäär. tarjous
    1 tarjoukset
    Locking into clock (verilog module) 6 päivää left
    VARMENNETTU

    I have a verilog model for digital data and clock recovery using DLL, the code needs debugging, so it needs someone who has a good background in this domain!

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    1 tarjoukset

    I have working verilog modules, need to convert to system verilog module and add UVM for test bench

    €141 (Avg Bid)
    €141 Keskimäär. tarjous
    1 tarjoukset
    Verilog HDL 5 päivää left

    building a simple hardware description of a sequential circuit in Verilog HDL which goal is to produce clock signals for serial communication baud rate generators.

    €74 (Avg Bid)
    €74 Keskimäär. tarjous
    13 tarjoukset

    Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.

    €249 (Avg Bid)
    €249 Keskimäär. tarjous
    5 tarjoukset

    Hi, i have this coding about image processing using verilog that i took from here [kirjaudu nähdäksesi URL:n] but i have a problem trying to make it synthesizable. Can you help me with that?

    €48 (Avg Bid)
    €48 Keskimäär. tarjous
    8 tarjoukset
    To Read accelerometer from Xilinx FPGA 4 päivää left
    VARMENNETTU

    Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

    €145 (Avg Bid)
    €145 Keskimäär. tarjous
    5 tarjoukset

    [kirjaudu nähdäksesi URL:n] and research paper Explanation [kirjaudu nähdäksesi URL:n] and PPT

    €123 (Avg Bid)
    €123 Keskimäär. tarjous
    2 tarjoukset
    VHDL using Xilinks 14.7 4 päivää left

    Using the Nexys 4 evaluation board implement a circuit, which presents on the 7-segment displays a “flying star” animated picture.

    €35 (Avg Bid)
    €35 Keskimäär. tarjous
    6 tarjoukset
    Need a VHDL coder 2 päivää left

    It does not have to be a perfect job, as long as it does its functions correctly.

    €156 (Avg Bid)
    €156 Keskimäär. tarjous
    11 tarjoukset
    FPGA bitstream for kawpow algorithm -- 2 2 päivää left
    VARMENNETTU

    I need someone who can Implement optimized bitsteam for both card types cvp13 as well as bcu1525 .As well as DNA locked pc [kirjaudu nähdäksesi URL:n] file. It should be a Bitsteam and miner application for both cvp13 and bcu1525. Kawpow algorithm minimum hashrate of 400mh for bcu and 650 for cvp I pay you 250 € after successful test From my experience guys are taking a pc miner ...

    €194 (Avg Bid)
    €194 Keskimäär. tarjous
    2 tarjoukset

    I have a verilog model for DLL and the model needs to modify it based on some requirements. This is simple task for the one who has a good background in this context but you will get benifit from continuing with me in this project

    €14 (Avg Bid)
    €14 Keskimäär. tarjous
    4 tarjoukset
    Counter modulo 7 2 päivää left

    Hello, Is there any VHDL expert to do my projet counter modulo 7 using VHDL. More details in the discussion

    €15 (Avg Bid)
    €15 Keskimäär. tarjous
    9 tarjoukset

    Anyone interest in building FPGA to mine bitcoin or other type of crypto currencies.

    €459 (Avg Bid)
    €459 Keskimäär. tarjous
    5 tarjoukset
    Modify LimeSDR FPGA 15 tuntia left

    The LimeSDR-USB allows to either transmit signals at once or schedule them. In all cases the samples must be passed from the host to the device at each call, which can take time due to the USB speed and latency. We would like to be able to just tell the device to transmit a specific type of signal, either at once or at a specific timestamp, without passing the samples each time. The different sig...

    €2565 (Avg Bid)
    €2565 Keskimäär. tarjous
    8 tarjoukset

    I need someone who knows verilog hdml, quartus and modelsim.

    €13 (Avg Bid)
    €13 Keskimäär. tarjous
    2 tarjoukset

    Multicycle project xilinix vhdl

    €29 (Avg Bid)
    €29 Keskimäär. tarjous
    4 tarjoukset

    Write 16 bit RISC processor verilog code and test bench code in structural programming. Explain the working of the code. Write a report of the project too. Don't write code in behavioral programming. Preferred software (ISE PROJECT NAVIGATOR)

    €84 (Avg Bid)
    €84 Keskimäär. tarjous
    2 tarjoukset

    Job Description :- We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating ...

    €446 (Avg Bid)
    €446 Keskimäär. tarjous
    10 tarjoukset

    Design a counter for the KL shopping mall entrances to allow maximum 99 shoppers at a time to promote social distancing. [Hints: Reset button can be used to clear the counter every morning; in/out signal can be used to control the up/down counter while people are moving in and out; red-light can be used to indicate whether they are allowed to enter] The report should include the following : -...

    €25 (Avg Bid)
    €25 Keskimäär. tarjous
    3 tarjoukset

    Parsing Infix notation to ONP i Verilog [FGPA] and calculating the value in two modules

    €25 (Avg Bid)
    €25 Keskimäär. tarjous
    2 tarjoukset
    Xilinx FPGA Expert Loppunut left

    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

    €472 (Avg Bid)
    €472 Keskimäär. tarjous
    5 tarjoukset

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    €120 (Avg Bid)
    €120 Keskimäär. tarjous
    5 tarjoukset

    I need someone who knows verilog hdml, quartus and modelsim.

    €18 (Avg Bid)
    €18 Keskimäär. tarjous
    8 tarjoukset
    Xilinx FPGA coding Loppunut left

    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

    €542 (Avg Bid)
    €542 Keskimäär. tarjous
    8 tarjoukset

    Skillset Requirements : - Work with Hardware and Design Engineer to define the Board Design Architecture, system requirements, component selections and implementation. - Accountable for developing FPGA designs, board bringup, retrospective, continuous improvements and documentation at system level. - Work on RTL coding using Verilog, performing simulations using ModelSim or QuestaSim, proficient i...

    €479 (Avg Bid)
    €479 Keskimäär. tarjous
    4 tarjoukset

    Debugging a clock recovery model in verilog

    €18 (Avg Bid)
    €18 Keskimäär. tarjous
    3 tarjoukset
    SMM Panel Server Loppunut left

    Need SMM panel with auto Facebook page likes, non dropped, all working, my own API. Something like: [url removed, login to view] Skills: Facebook Marketing, Landing Pages, PHP, Software Architecture, Web Scraping See more: oprogramowanie c++ freelance, freelancer oprogramowanie, grafik freelancer oprogramowanie, oprogramowanie vhdl, napisz, Napisz oprogramowanie, i am looking to get a working fa...

    €119 (Avg Bid)
    €119 Keskimäär. tarjous
    6 tarjoukset

    Do NOT big if you don't have the knowledge. This task is simple but it needs some background so you don't have to spend too much time to think about it if you have the strong knowledge ok! I have a model for a clock recovery including encoder/decoder with the emphasis to the decoder, the decoder needs to estimate the clock from the data, the model already does this job but I need to add ...

    €15 (Avg Bid)
    €15 Keskimäär. tarjous
    6 tarjoukset
    Verilog coding Loppunut left

    write a verilog code from RAM using icaurus verilog

    €5 / hr (Avg Bid)
    €5 / hr Keskimäär. tarjous
    5 tarjoukset

    8 point fft algorithm using verilog [kirjaudu nähdäksesi URL:n] complete explanation for the project (what is done, brief explanation and why it is done) [kirjaudu nähdäksesi URL:n] explanation for the base paper [kirjaudu nähdäksesi URL:n] for the code

    €13 (Avg Bid)
    €13 Keskimäär. tarjous
    2 tarjoukset
    €30 Keskimäär. tarjous
    5 tarjoukset

    Practical FPGA Design and Interfacing Structure of exam: Programming using Quartus Prime Software : Quartus Prime 18.1 Language: Verilog HDL

    €105 (Avg Bid)
    €105 Keskimäär. tarjous
    7 tarjoukset

    Subject:Practical FPGA Design and Interfacing Topic cover : State machine Structure: Programming using Quartus Prime

    €101 (Avg Bid)
    €101 Keskimäär. tarjous
    7 tarjoukset

    Microcontrollers and FPGA Expert

    €20 (Avg Bid)
    €20 Keskimäär. tarjous
    1 tarjoukset
    verilog calculator Loppunut left

    Verilog simple calculator using FPGA with 4x4 keypad and 7 segment display

    €93 (Avg Bid)
    €93 Keskimäär. tarjous
    8 tarjoukset

    We need a engineer to help make fpga design for carrier board,if you have experience to do this job,then please contact me,thanks.

    €138 (Avg Bid)
    €138 Keskimäär. tarjous
    5 tarjoukset

    Expert in FPGA-Xilinc ARTY A7-100 T and RISC-V for correcting a design model.

    €42 (Avg Bid)
    €42 Keskimäär. tarjous
    2 tarjoukset

    I need help with verilog code, and PICSIMLab

    €14 (Avg Bid)
    €14 Keskimäär. tarjous
    6 tarjoukset

    To develop the firmware that is able to display single image sequence in GIF format, using a development board based at Spartan 6-7 and a couple of LED panels. Language: System Verilog only (!)

    €476 (Avg Bid)
    €476 Keskimäär. tarjous
    3 tarjoukset

    Expert trainer in FPGA-Xilinc ARTY A7-100 T and RISC-V for 5 hours in supporting a design model. Per hour $2 to $5.

    €8 - €25
    €8 - €25
    0 tarjoukset

    I need a Verilog programmer for a short project.

    €13 / hr (Avg Bid)
    €13 / hr Keskimäär. tarjous
    11 tarjoukset

    To design convolutional neural network with various techniques (simple loops, with hardware loops, with loop unrolling and the combination of hardware loops and loop unrolling) using python, to convert the python code to verilog HDL and implement it using fpga.

    €190 (Avg Bid)
    €190 Keskimäär. tarjous
    4 tarjoukset
    verilog programming Loppunut left

    I need a good verilog programmer who is also good at arduino

    €16 / hr (Avg Bid)
    €16 / hr Keskimäär. tarjous
    9 tarjoukset

    need to build a basic football game on FPGA and Xilinx. left side of the screen will be goal of one of the player and right side the other. Need to set 2 button. One of them for one player and one of them for other. In the middle there will be number 1 and it goes left and then to right. When it goes to left and player press the button, that number 1 will go right side. Therefore, players will be ...

    €73 (Avg Bid)
    €73 Keskimäär. tarjous
    4 tarjoukset
    I need a VHDL coder Loppunut left

    Implement Carry select adder using pipeline input is two 16 bits you are supposed to pipeline this

    €77 (Avg Bid)
    €77 Keskimäär. tarjous
    8 tarjoukset
    €51 Keskimäär. tarjous
    5 tarjoukset

    This project needs Xilinx for coding for hardware modeling and design and implementation of 4 bit ALU. It needs to be done in next 24 hours. Please inbox me further details.

    €31 (Avg Bid)
    €31 Keskimäär. tarjous
    7 tarjoukset

    Simscape Simulation, GUI, Matlab Basically it is about linear actuator and I am using stepper motor (Complete: 10 June 2021 (Malaysian Time 12pm) (When Start Give Progress Everyday) (Make sure no copy paste codes or anything from any internet sources) Watch this youtube video basically it like this but I am using component in my proposal [kirjaudu nähdäksesi URL:n] This project basi...

    €163 (Avg Bid)
    €163 Keskimäär. tarjous
    12 tarjoukset