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    4,646 verilog vhdl työtä löytyi, hinnoittelu EUR
    Simple VHDL task Loppunut left

    Simple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL task

    €85 (Avg Bid)
    €85 Keskimäär. tarjous
    1 tarjoukset

    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. It is a short program to be implemented in VHDL, preferably using GHDL in Linux. Would you be interested? You seem very knowledgable in the area

    €47 (Avg Bid)
    €47 Keskimäär. tarjous
    1 tarjoukset

    Hi Aamir Sohail N., I noticed your profile and would like to offer you my project. It is a quick task in VHDL, I can send the documentation on what needs to be done

    €38 (Avg Bid)
    €38 Keskimäär. tarjous
    1 tarjoukset
    Project for Duc D. 8 päivää left

    Hi Duc D., I noticed your profile and would like to offer you my project. It is a quick task in VHDL, I can send the documentation on what needs to be done

    €40 (Avg Bid)
    €40 Keskimäär. tarjous
    1 tarjoukset
    Project for Mairaj A. 8 päivää left

    Hi Mairaj A., I noticed your profile and would like to offer you my project. It is a very quick task in VHDL, would you be interested? I can send the sheet on that needs to be done

    €34 (Avg Bid)
    €34 Keskimäär. tarjous
    1 tarjoukset
    Verilog Coding 5 päivää left

    We need to program a FPGA board using verilog code with XNOR, Multiply, shiftleft and add modules that can run on the board using different switches. When we compile the code there are no errors but when we try to put the code onto the board it is showing only zeros so we think that there is something wrong with the XNOR, Mul, shiftleft or ADD modules. I will attach all codes and the manual for the project below, thanks.

    €102 (Avg Bid)
    €102 Keskimäär. tarjous
    4 tarjoukset

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    €52 (Avg Bid)
    €52 Keskimäär. tarjous
    1 tarjoukset

    The entire description of the project is in the file below Circuit modeling in

    €173 (Avg Bid)
    €173 Keskimäär. tarjous
    7 tarjoukset

    Write the equivalent VHDL code, and Verify the correct operation through Vivado Simulator by comparing your simulation results with those of MARS runs.

    €73 (Avg Bid)
    €73 Keskimäär. tarjous
    4 tarjoukset
    €159 Keskimäär. tarjous
    3 tarjoukset

    I need to implement digital signature algorithm in Xilinx Vivado Design Suite using Verilog. Please find the attachment for complete details of project.

    €277 (Avg Bid)
    €277 Keskimäär. tarjous
    4 tarjoukset

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    €19 / hr (Avg Bid)
    €19 / hr Keskimäär. tarjous
    1 tarjoukset

    I want to create programming routines to be recorded on an FPGA

    €30 / hr (Avg Bid)
    €30 / hr Keskimäär. tarjous
    15 tarjoukset

    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

    €30 (Avg Bid)
    €30 Keskimäär. tarjous
    5 tarjoukset

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    €15 / hr (Avg Bid)
    €15 / hr Keskimäär. tarjous
    1 tarjoukset

    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

    €36 (Avg Bid)
    €36 Keskimäär. tarjous
    6 tarjoukset
    servomotor in vhdl Loppunut left

    separate project in 3rd part, first make the chdl codes according to the state machine as well as their test ban (Reception and emission), make a top entity etc...

    €41 (Avg Bid)
    €41 Keskimäär. tarjous
    5 tarjoukset

    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

    €137 (Avg Bid)
    €137 Keskimäär. tarjous
    14 tarjoukset

    Hi Mohammed Ibrahim, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    €47 (Avg Bid)
    €47 Keskimäär. tarjous
    1 tarjoukset

    Hi Mohammed Ibrahim, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    €47 (Avg Bid)
    €47 Keskimäär. tarjous
    1 tarjoukset

    I want to use accelerometer sensor on FPGA, in order to do that I need I2C protocol implementation in VHDL so I can continue my work on the project. I want the module to get the address of the sensor + bit for R/W , and the internal register address of the sensor, and get the data by reading, or write to the register.

    €252 (Avg Bid)
    €252 Keskimäär. tarjous
    13 tarjoukset

    Hi there Urgently need small VHDL project to be done. Please apply ASAP if you can start it immediately after hiring Thanks

    €102 (Avg Bid)
    €102 Keskimäär. tarjous
    4 tarjoukset

    Using the fixed point arithmetic measure current according to the following circuit

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    6 tarjoukset

    Hi there Urgently need small VHDL project to be done. Please apply ASAP if you can start it immediately after hiring Thanks

    €287 (Avg Bid)
    €287 Keskimäär. tarjous
    5 tarjoukset

    Create a VHDL routine to water a plant using state machines and a specific board

    €32 / hr (Avg Bid)
    €32 / hr Keskimäär. tarjous
    10 tarjoukset

    Instruction Decoder and ALU Control In this lab, students are expected to implement an instruction decoder and an ALU control unit using VHDL in the Xilinx software. The purpose of the instruction decoder is to generate proper control signals based on the Opcode of an instruction fetched from the instruction memory. The purpose of the ALU control is to set the proper ALU control signal based on the Funct field of an instruction and the ALUOp signal from the instruction decoder.

    €143 (Avg Bid)
    €143 Keskimäär. tarjous
    17 tarjoukset

    I need to design gradient descent optimizer on FPGA in verilog language and code should be synthesizable. entire design should be pipelined. Input and outputs should be in single precision floating point representation. loss or cost function is mean square error loss for 2D variables, minimise the above cost functions to achieve the optimised value. I have developed gradient descent optImizer on python , below attached file is code of it. I want same implementation in verilog

    €137 (Avg Bid)
    €137 Keskimäär. tarjous
    6 tarjoukset

    Good knowledge of VHDL is required. Libero Soc and Microsemi will be used The simulator will be Aldec Active-HDL, linting with Aldec Alint Design of a basic control board, standard interfaces, no high speed interfaces, no transceivers. DO-254 DAL C, basic knowledge is a plus some math algorithm in fixed point will be implemented on the hardware for motor control Supervision of our expert designers, short daily meeting and 1h weekly with reports on activities and scheduling contract will be extended month by month (we have budget for 6 months).

    €225 / hr (Avg Bid)
    €225 / hr Keskimäär. tarjous
    5 tarjoukset

    1- Signal processing using ML on a computer (C Language) 2- using Single and dual ARM (C Language) 3-using FPGA Zedboard programmable logic (VHDL Language)

    €189 (Avg Bid)
    €189 Keskimäär. tarjous
    12 tarjoukset
    Verilog Coding Loppunut left

    My project includes working on a verilog code for a stair case encoder. Below is the image of the architecture of the encoder and for each seperate block, i need codes for it. A full description of the project will be given to you in the form of a research paper. If you know how to write codes in verilog, kindly contact me. We can discuss more about the project as I have already done a small part of it and need help for the rest of the blocks. Price is negotiable. Thank you.

    €94 (Avg Bid)
    €94 Keskimäär. tarjous
    3 tarjoukset

    Verilog Vivado Software Basys3 Board

    €26 (Avg Bid)
    €26 Keskimäär. tarjous
    2 tarjoukset

    Hi! I need in System Verilog this: A module that receives 16bits 1 bit for positive or negative number and 15 bits for number then the module is going to create the BCD for all the possibilities negotiable payment!

    €9 (Avg Bid)
    €9 Keskimäär. tarjous
    1 tarjoukset
    verilog programming Loppunut left

    Hoy I need in System Verilog this: A module that receives 16bits 1 bit for positive or negative number and 15 bits for number then the module is going to create the BCD for all the possibilities this is a project in SystemVerilog using Nexys4 negotiable payment!

    €9 (Avg Bid)
    €9 Keskimäär. tarjous
    1 tarjoukset

    I need in System Verilog this: A module that receives 16bits 1 bit for positive or negative number and 15 bits for number then the module is going to create the BCD for all the possibilities this is a project in SystemVerilog using Nexys4

    €5 / hr (Avg Bid)
    €5 / hr Keskimäär. tarjous
    1 tarjoukset

    I'm trying to solve 5*5 grid tic tac toe game using Verilog, i need help in developing the tic tac toe game for 5*5 grid

    €98 (Avg Bid)
    €98 Keskimäär. tarjous
    3 tarjoukset

    i want code and report. I need plagiarism free report. software is quatrus

    €7 / hr (Avg Bid)
    €7 / hr Keskimäär. tarjous
    2 tarjoukset

    i want code and report. I need plagiarism free report. software is quatrus

    €7 / hr (Avg Bid)
    €7 / hr Keskimäär. tarjous
    3 tarjoukset

    Hi developers. I am looking for quick help for System Verilog code help. Please apply if you are expert in Verilog. Thanks.

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    9 tarjoukset

    I have a localparamter declared in my SystemVerilog like this (y is another Parameter) : localparam x = y ? 4 : 1 , Then I have a RTL port which is something like this (where z is another parameter): input logic [x-1:0][((z+1)*8-1):0] port1, But I want to use 'y' directly in this port1 instead of x. Can I somehow use 'y' instead of x to dynamically allocate the value of it. It should be able to compile/elaborate. Should be quick

    €27 (Avg Bid)
    €27 Keskimäär. tarjous
    4 tarjoukset

    Besides the system consisting of the data buffer, you should also design a test bench to simulate the three external systems.

    €129 (Avg Bid)
    €129 Keskimäär. tarjous
    16 tarjoukset

    A VHDL project about producing Moors code and converting it to ASCI code needs to be improved since it does not produce correct results.

    €170 (Avg Bid)
    €170 Keskimäär. tarjous
    14 tarjoukset

    Verilog FPGA programming in Linux

    €29 (Avg Bid)
    €29 Keskimäär. tarjous
    4 tarjoukset

    Computer engineering freelancer project with Verilog.

    €76 (Avg Bid)
    €76 Keskimäär. tarjous
    1 tarjoukset

    ASIC Acceleration for Graph Convolutional Neural Networks (GCNs) The task is to write a verilog code use that instantiates the GCN module. This verilog code check the correctness of the module with behavioral, post-synthesis, and post-Innovus Verilog netlists. Rest of the documents will be provided in the chat.

    €78 (Avg Bid)
    €78 Keskimäär. tarjous
    5 tarjoukset

    Make the RED square move and if its hits any of the sides, then the player loses the game. Add a graphic indicating the player lost. Add a points keeping system on the screen or FPGA

    €97 (Avg Bid)
    €97 Keskimäär. tarjous
    8 tarjoukset
    verilog coding game Loppunut left

    Make the RED square move and if its hits any of the sides, then the player loses the game. Add a graphic indicating the player lost. Add a points keeping system on the screen or FPGA

    €96 (Avg Bid)
    €96 Keskimäär. tarjous
    12 tarjoukset

    Deadline is in 2 days Details will be trough the chat Please bid and I'll get back to u Thanks

    €25 (Avg Bid)
    €25 Keskimäär. tarjous
    11 tarjoukset

    I need a 2 second counter on switch 0, switch 1, switch 2, switch 3, switch 4. If either of these switches are open it will give logic level 1 and will feed into an AND GATE. If switches open and closes with 2 seconds, it will not give logic level 1. Switch 5 will already be give logic level 1 to AND GATE when it is opened. When AND GATE output is high, it will turn on LED. I need to write this code in verily.

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    7 tarjoukset

    Need a VHDL and FPGA Systems expert 1. To create a modular system using VHDL. 2. To use simulation and test to verify the correctness of the design. 3. To demonstrate the milestones working on a target FPGA device. 4. To document the entire design process - recording the technical detail and justification of the work done. Detailed document will be provided on chat

    €143 (Avg Bid)
    €143 Keskimäär. tarjous
    12 tarjoukset