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    2,767 verilog vhdl työtä löytyi, hinnoittelu EUR
    Simple VHDL task Loppunut left

    Simple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL task

    €78 (Avg Bid)
    €78 Keskimäär. tarjous
    1 tarjoukset
    Task on verilog 3 bit ALU 6 päivää left
    VARMENNETTU

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    €38 (Avg Bid)
    €38 Keskimäär. tarjous
    11 tarjoukset

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    3 tarjoukset
    Distance using FPGA 4 päivää left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    €110 (Avg Bid)
    €110 Keskimäär. tarjous
    19 tarjoukset

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    €14 / hr (Avg Bid)
    €14 / hr Keskimäär. tarjous
    26 tarjoukset

    I have project ready already just need some help!

    €167 (Avg Bid)
    €167 Keskimäär. tarjous
    9 tarjoukset
    SRAM FPGA controller in Verilog 22 tuntia left
    VARMENNETTU

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    €16 (Avg Bid)
    €16 Keskimäär. tarjous
    6 tarjoukset

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    €28 (Avg Bid)
    €28 Keskimäär. tarjous
    3 tarjoukset

    risc processor design and test, more detail I will provide on chat

    €91 (Avg Bid)
    €91 Keskimäär. tarjous
    16 tarjoukset

    Create a custom SPI master controller with single, dual, and QUAD operation modes in VHDL for a MAX V CPLD.

    €337 (Avg Bid)
    €337 Keskimäär. tarjous
    9 tarjoukset

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    €121 (Avg Bid)
    €121 Keskimäär. tarjous
    7 tarjoukset

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €104 (Avg Bid)
    €104 Keskimäär. tarjous
    17 tarjoukset

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    €431 (Avg Bid)
    €431 Keskimäär. tarjous
    15 tarjoukset

    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    €37 (Avg Bid)
    €37 Keskimäär. tarjous
    13 tarjoukset

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €152 (Avg Bid)
    €152 Keskimäär. tarjous
    12 tarjoukset

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €129 (Avg Bid)
    €129 Keskimäär. tarjous
    4 tarjoukset

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €357 (Avg Bid)
    €357 Keskimäär. tarjous
    2 tarjoukset
    Vhdl LCD finctional Loppunut left

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [kirjaudu nähdäksesi URL:n]

    €28 (Avg Bid)
    €28 Keskimäär. tarjous
    5 tarjoukset
    DSP48E1 help Loppunut left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
    €3 / hr Keskimäär. tarjous
    5 tarjoukset

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    €180 (Avg Bid)
    €180 Keskimäär. tarjous
    12 tarjoukset
    I want clients Loppunut left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €16 (Avg Bid)
    €16 Keskimäär. tarjous
    2 tarjoukset

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    €16 / hr (Avg Bid)
    €16 / hr Keskimäär. tarjous
    10 tarjoukset

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €133 (Avg Bid)
    €133 Keskimäär. tarjous
    7 tarjoukset

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    €447 (Avg Bid)
    €447 Keskimäär. tarjous
    10 tarjoukset

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

    €96 (Avg Bid)
    €96 Keskimäär. tarjous
    1 tarjoukset

    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

    €22 (Avg Bid)
    €22 Keskimäär. tarjous
    2 tarjoukset

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

    €31 (Avg Bid)
    €31 Keskimäär. tarjous
    2 tarjoukset

    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    3 tarjoukset

    I need help with the structural in Xilinx. I will give you full details. Regards

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    23 tarjoukset

    ...am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    111 tarjoukset

    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

    €50 (Avg Bid)
    €50 Keskimäär. tarjous
    1 tarjoukset
    verilog project Loppunut left

    verilog coding using putty or terminal. if you are interested i will give more information.

    €117 (Avg Bid)
    €117 Keskimäär. tarjous
    27 tarjoukset
    System verilog Loppunut left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €84 (Avg Bid)
    €84 Keskimäär. tarjous
    8 tarjoukset

    Implement an AD2949 IC input block and some more

    €457 (Avg Bid)
    €457 Keskimäär. tarjous
    11 tarjoukset
    verilog project Loppunut left

    mtech Verilog project

    €18 (Avg Bid)
    €18 Keskimäär. tarjous
    19 tarjoukset

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €155 (Avg Bid)
    €155 Keskimäär. tarjous
    7 tarjoukset

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2442 (Avg Bid)
    €2442 Keskimäär. tarjous
    15 tarjoukset

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    €90 (Avg Bid)
    €90 Keskimäär. tarjous
    12 tarjoukset

    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

    €72 (Avg Bid)
    €72 Keskimäär. tarjous
    21 tarjoukset

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    €87 (Avg Bid)
    €87 Keskimäär. tarjous
    2 tarjoukset

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €17 / hr (Avg Bid)
    €17 / hr Keskimäär. tarjous
    9 tarjoukset
    verilog assignment Loppunut left

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €113 (Avg Bid)
    €113 Keskimäär. tarjous
    12 tarjoukset
    PRESENT-80 Loppunut left

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

    €47 (Avg Bid)
    €47 Keskimäär. tarjous
    4 tarjoukset

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

    €26 (Avg Bid)
    €26 Keskimäär. tarjous
    2 tarjoukset

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3828 (Avg Bid)
    €3828 Keskimäär. tarjous
    27 tarjoukset

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €337 (Avg Bid)
    €337 Keskimäär. tarjous
    3 tarjoukset

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

    €136 (Avg Bid)
    €136 Keskimäär. tarjous
    9 tarjoukset

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    €56 (Avg Bid)
    €56 Keskimäär. tarjous
    18 tarjoukset
    need expert on VHDL Loppunut left

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    €63 (Avg Bid)
    €63 Keskimäär. tarjous
    20 tarjoukset

    build a communication block in VHDL at Xilinx environment

    €347 (Avg Bid)
    €347 Keskimäär. tarjous
    14 tarjoukset