Verilog project työt

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    1,385 verilog project työtä löytyi, hinnoittelu EUR

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    €68 (Avg Bid)
    €68 Keskimäär. tarjous
    5 tarjoukset
    Task on verilog 3 bit ALU 3 päivää left
    VARMENNETTU

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    €51 (Avg Bid)
    €51 Keskimäär. tarjous
    20 tarjoukset

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    3 tarjoukset
    Distance using FPGA 20 tuntia left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    €102 (Avg Bid)
    €102 Keskimäär. tarjous
    21 tarjoukset

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    €14 / hr (Avg Bid)
    €14 / hr Keskimäär. tarjous
    30 tarjoukset

    I have project ready already just need some help!

    €169 (Avg Bid)
    €169 Keskimäär. tarjous
    9 tarjoukset

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    6 tarjoukset

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    €29 (Avg Bid)
    €29 Keskimäär. tarjous
    3 tarjoukset

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    €122 (Avg Bid)
    €122 Keskimäär. tarjous
    7 tarjoukset

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €106 (Avg Bid)
    €106 Keskimäär. tarjous
    17 tarjoukset

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    €436 (Avg Bid)
    €436 Keskimäär. tarjous
    15 tarjoukset

    Please refer the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    €38 (Avg Bid)
    €38 Keskimäär. tarjous
    13 tarjoukset

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €154 (Avg Bid)
    €154 Keskimäär. tarjous
    12 tarjoukset

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €130 (Avg Bid)
    €130 Keskimäär. tarjous
    4 tarjoukset

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €361 (Avg Bid)
    €361 Keskimäär. tarjous
    2 tarjoukset
    DSP48E1 help Loppunut left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
    €3 / hr Keskimäär. tarjous
    5 tarjoukset
    I want clients Loppunut left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €16 (Avg Bid)
    €16 Keskimäär. tarjous
    2 tarjoukset

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €133 (Avg Bid)
    €133 Keskimäär. tarjous
    7 tarjoukset

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    111 tarjoukset
    verilog project Loppunut left

    verilog coding using putty or terminal. if you are interested i will give more information.

    €118 (Avg Bid)
    €118 Keskimäär. tarjous
    27 tarjoukset
    System verilog Loppunut left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €85 (Avg Bid)
    €85 Keskimäär. tarjous
    8 tarjoukset
    verilog project Loppunut left

    mtech Verilog project

    €18 (Avg Bid)
    €18 Keskimäär. tarjous
    19 tarjoukset

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €157 (Avg Bid)
    €157 Keskimäär. tarjous
    7 tarjoukset

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2470 (Avg Bid)
    €2470 Keskimäär. tarjous
    15 tarjoukset

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    €91 (Avg Bid)
    €91 Keskimäär. tarjous
    12 tarjoukset

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    €88 (Avg Bid)
    €88 Keskimäär. tarjous
    2 tarjoukset

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €17 / hr (Avg Bid)
    €17 / hr Keskimäär. tarjous
    9 tarjoukset
    verilog assignment Loppunut left

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €114 (Avg Bid)
    €114 Keskimäär. tarjous
    12 tarjoukset

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3872 (Avg Bid)
    €3872 Keskimäär. tarjous
    27 tarjoukset

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €340 (Avg Bid)
    €340 Keskimäär. tarjous
    3 tarjoukset

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    €57 (Avg Bid)
    €57 Keskimäär. tarjous
    18 tarjoukset

    FPGA TCPIP implementation using Verilog

    €18 / hr (Avg Bid)
    €18 / hr Keskimäär. tarjous
    16 tarjoukset

    Verilog digital logic deisgn simple work

    €20 (Avg Bid)
    €20 Keskimäär. tarjous
    18 tarjoukset

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [kirjaudu nähdäksesi URL:n]

    €40 (Avg Bid)
    €40 Keskimäär. tarjous
    16 tarjoukset

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    €20 (Avg Bid)
    €20 Keskimäär. tarjous
    21 tarjoukset

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    €19 (Avg Bid)
    €19 Keskimäär. tarjous
    17 tarjoukset

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    €18 / hr (Avg Bid)
    €18 / hr Keskimäär. tarjous
    20 tarjoukset

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    €114 (Avg Bid)
    €114 Keskimäär. tarjous
    19 tarjoukset

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    €106 (Avg Bid)
    €106 Keskimäär. tarjous
    13 tarjoukset

    We are looking for a System Verilog Training for few Engineers in our premises.

    €1735 (Avg Bid)
    €1735 Keskimäär. tarjous
    5 tarjoukset

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    €87 (Avg Bid)
    €87 Keskimäär. tarjous
    8 tarjoukset

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    €106 (Avg Bid)
    €106 Keskimäär. tarjous
    19 tarjoukset
    Alarm clock Verilog Loppunut left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    €161 (Avg Bid)
    €161 Keskimäär. tarjous
    15 tarjoukset

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    €75 (Avg Bid)
    €75 Keskimäär. tarjous
    5 tarjoukset

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    €93 (Avg Bid)
    €93 Keskimäär. tarjous
    11 tarjoukset

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €115 (Avg Bid)
    €115 Keskimäär. tarjous
    7 tarjoukset

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [kirjaudu nähdäksesi URL:n] Using PG236 [kirjaudu nähdäksesi URL:n]

    €112 (Avg Bid)
    €112 Keskimäär. tarjous
    3 tarjoukset

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    €63 (Avg Bid)
    €63 Keskimäär. tarjous
    1 tarjoukset

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    €37 / hr (Avg Bid)
    €37 / hr Keskimäär. tarjous
    1 tarjoukset
    Image encryption Loppunut left

    I need image encryption using verilog on FPGA board

    €701 (Avg Bid)
    €701 Keskimäär. tarjous
    13 tarjoukset