Suodata

Viimeisimmät hakuni
Suodatusperuste:
Budjetti
asti
asti
asti
Tyyppi
Taidot
Kielet
    Työn tila
    4,856 verilog ascii työtä löytyi, hinnoittelu EUR

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    €25 (Avg Bid)
    €25 Keskimäär. tarjous
    16 tarjoukset

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    €491 (Avg Bid)
    €491 Keskimäär. tarjous
    11 tarjoukset
    Web Browser Loppunut left

    ...<p> you should insert a blank line in the output. The HTTP GET command needs to be followed by two control (CR) linefeed (LF) pairs in HTTP version 1.0. CR is ASCII value 13, linefeed is ASCII value 10. The web server (csweb01) will be listening to port 80 (the standard port). You will show that your browser works by displaying a few web pages, following

    €126 (Avg Bid)
    €126 Keskimäär. tarjous
    5 tarjoukset
    €70 Keskimäär. tarjous
    1 tarjoukset
    ASCII GIF display Loppunut left

    Develop software in assemly that will convert gif into ASCII art.

    €175 (Avg Bid)
    €175 Keskimäär. tarjous
    3 tarjoukset

    ...my project. We can discuss any details over chat. assembly language program that will ask the user to enter the name of a text file with file extension .txt that contains ASCII encoded text. Then the program will process the file to count the number and type of characters in it, and then display on the screen the statistics counted from the file.

    €218 (Avg Bid)
    €218 Keskimäär. tarjous
    1 tarjoukset
    Write some software Loppunut left

    I need you to develop some software for me. I would like this software to be developed for Windows using Java. A generic Jav...players and telnet clients that can be used to connect to the server and send / receive game’s instructions. The game clients communicates with the server using single lines of ASCII text messages, sent to the board server.

    €137 (Avg Bid)
    €137 Keskimäär. tarjous
    8 tarjoukset

    Write a windows program to corrupt/garble/jumble a file (text,ANSI, ASCII, Unicode, binary etc) and restore the original file back when required using command line.

    €93 (Avg Bid)
    €93 Keskimäär. tarjous
    7 tarjoukset

    Hi, I want a 2D convolution module in Verilog, using DSPs.

    €39 (Avg Bid)
    €39 Keskimäär. tarjous
    8 tarjoukset
    Quartus Loppunut left

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    2 tarjoukset

    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

    €93 (Avg Bid)
    €93 Keskimäär. tarjous
    10 tarjoukset
    Project for Alka R. Loppunut left

    Hi Alka, I am looking for someone to do an easy but comber...meteorological data, global and I only need the time series of two points, an ensemble, the data consists of an ensemble of 30 runs and from each I just need those 2 points in ascii or some other easy to access format. I think it should not take more than 5 hours but it will depend of course

    €51 (Avg Bid)
    €51 Keskimäär. tarjous
    1 tarjoukset

    Interface between MCU / SDR for conversion of raw data to ASCII format and posting to http post. Polling algorithm with sending and ACK protocols

    €241 (Avg Bid)
    €241 Keskimäär. tarjous
    6 tarjoukset

    Required a small class file .net 4.5 c# to convert a .jpg file or font file to a structured ascii data and produce a zpl string to send to a printer. Documentation for the requirements on the converted files and the zpl commands are in the attached file. Class must accept a file location for the file to be converted, file location for on the printer

    €186 (Avg Bid)
    €186 Keskimäär. tarjous
    6 tarjoukset

    Need a serial multiplier coded in system verilog

    €109 (Avg Bid)
    €109 Keskimäär. tarjous
    3 tarjoukset

    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    6 tarjoukset

    i need a code for serial multiplier using verilog not from online please

    €37 (Avg Bid)
    €37 Keskimäär. tarjous
    12 tarjoukset

    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

    €94 (Avg Bid)
    €94 Keskimäär. tarjous
    10 tarjoukset

    For a security application, a Flash-Storage SST26VF016B was desoldered from a printed circuit board and ad...content over the UART Interface in HEX. Also need to develop an additional routine where the content of each register will only be displayed if the read byte is a readable (ASCII) character (0-9 and a-Z), discard the other unreadable bytes.

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    4 tarjoukset
    Reading Pcap file Loppunut left

    ...lidar data must be read and converted to ASCII file using the manuel of lidar. Firstly, the software will reach the packets in the pcap. Secondly, the packets must converted to values ( time, azimuth, lase ID etc.) with respect to the Velodyne Manuel. As a result, after processing a pcap file, I have to get a ASCII file contains the values of measurements

    €20 (Avg Bid)
    €20 Keskimäär. tarjous
    3 tarjoukset

    i need a verilog code for serial multipler

    €27 (Avg Bid)
    €27 Keskimäär. tarjous
    8 tarjoukset

    Need help cleaning up some code, and matrix multiplication.

    €44 (Avg Bid)
    €44 Keskimäär. tarjous
    7 tarjoukset

    hi, looking for an IoS app development - with 3 to4 GUI screen , provision for the user to key in ascii values and send the data over Wi-Fi interface to open Access point unit in sight also read back from the Access point and display.

    €13 / hr (Avg Bid)
    €13 / hr Keskimäär. tarjous
    1 tarjoukset
    EEG to ASCII Loppunut left

    need a neural network that can identify brain signals into ASCII text. My hardware is epoc emotiv and i have the emokit working with it on linux.

    €739 (Avg Bid)
    €739 Keskimäär. tarjous
    14 tarjoukset

    I need Verilog Code for BMI calculation that can be running in Quartus software.

    €123 (Avg Bid)
    €123 Keskimäär. tarjous
    2 tarjoukset

    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    5 tarjoukset

    ...parity No flow control 115.2k baud The local host is accessing the pi using serial code written in php is done. Raspberry pi send data from local host in form of ASCII characters to the terminal (like teraterm and hyperterm) and get response back at local host-- Done We have already set all specifications for Mini com and terminal communication

    €29 / hr (Avg Bid)
    €29 / hr Keskimäär. tarjous
    11 tarjoukset

    We require a simple oscilloscope project to be implemented using only Verilog code on DE1-SoC board by the latest date of 7th of May as agreed during the chat conversation. This project will comprise of modular Verilog code, fully commented, test-benches for verification and a technical report of the project. Altera Quartus software will be used for

    €183 (Avg Bid)
    €183 Keskimäär. tarjous
    1 tarjoukset
    Need a programmer Loppunut left

    We require a small program to be written that converts file ...require a small program to be written that converts file formats between two ASCII formatted files. The files are basically a list of co-ordinates that are used for a flight plan for a UAV, and we require the co-ordinates to be read and written out in two different ascii formats.

    €134 (Avg Bid)
    €134 Keskimäär. tarjous
    17 tarjoukset

    A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

    €191 (Avg Bid)
    €191 Keskimäär. tarjous
    11 tarjoukset

    I want Verilog expert to help in some projects

    €70 (Avg Bid)
    €70 Keskimäär. tarjous
    1 tarjoukset

    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    €68 (Avg Bid)
    €68 Keskimäär. tarjous
    1 tarjoukset

    more details will be given in the chat

    €20 (Avg Bid)
    €20 Keskimäär. tarjous
    1 tarjoukset

    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language

    €111 (Avg Bid)
    €111 Keskimäär. tarjous
    11 tarjoukset

    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

    €303 (Avg Bid)
    €303 Keskimäär. tarjous
    3 tarjoukset
    Verilog coding Loppunut left

    Verilog code of Simplified DES algorithm

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    9 tarjoukset

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €250 (Avg Bid)
    €250 Keskimäär. tarjous
    10 tarjoukset

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

    €147 (Avg Bid)
    €147 Keskimäär. tarjous
    5 tarjoukset

    ...PHP Socket programming send and receive Data project. Description: - I have a dedicated php server hosted on cloud (GoDaddy) - I have an external modem which can send ascii data string on this server's ip on a specific port. - I need a program to capture the data stream on using sockets to capture data on specific tcp port and capture the data

    €101 (Avg Bid)
    €101 Keskimäär. tarjous
    4 tarjoukset

    ...YOU able to integrate merchant accounts with shopping cart? i will receive the data in the following formats. • Comma delimited • Pipe delimited | • Tab delimited Ascii Char 9 are you able to work with that? at present the site is is built on a template, will you format it to what i need to sell including categories etc? Also i will need

    €17 / hr (Avg Bid)
    €17 / hr Keskimäär. tarjous
    43 tarjoukset

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    €138 (Avg Bid)
    €138 Keskimäär. tarjous
    16 tarjoukset

    ...returns a list where all uppercase letters have been converted to lowercase letters. Hint: The ML functions ord and chr could be useful here, as would the knowledge of the ASCII values for A and a. The function call changeToLowercase [#”a”, #”A”] should return [#”a”, #”a”] d. getLast: given a list, this function returns the last i...

    €26 (Avg Bid)
    €26 Keskimäär. tarjous
    3 tarjoukset

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    €100 (Avg Bid)
    €100 Keskimäär. tarjous
    9 tarjoukset
    200418_Verilog Loppunut left
    VARMENNETTU

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    €44 - €70
    Sinetöity
    €44 - €70
    4 tarjoukset

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    €339 (Avg Bid)
    €339 Keskimäär. tarjous
    6 tarjoukset

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    €26 (Avg Bid)
    €26 Keskimäär. tarjous
    11 tarjoukset

    Tcp sending on FPGA using verilog xgmii xilinx vivado

    €357 (Avg Bid)
    €357 Keskimäär. tarjous
    4 tarjoukset

    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    €363 (Avg Bid)
    €363 Keskimäär. tarjous
    5 tarjoukset
    verilog expert only Loppunut left

    more details will be given in the chat

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    14 tarjoukset