Outsource asic vlsi fpga verilog vhdl työt

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    5,447 outsource asic vlsi fpga verilog vhdl työtä löytyi, hinnoittelu EUR
    €98 Keskimäär. tarjous
    1 tarjoukset
    Simple VHDL task Loppunut left

    Simple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL taskSimple VHDL task

    €79 (Avg Bid)
    €79 Keskimäär. tarjous
    1 tarjoukset

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    €62 - €123
    €62 - €123
    0 tarjoukset

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) Look at the problems in: [kirjaudu nähdäksesi URL:n] WILL PAY GENEROUSLY. $$$ Project Description is: [kirjaudu nähdäksesi URL:n] Reference Literature: CMOS VLSI Design Happy Bidding

    €9 - €176
    €9 - €176
    0 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €149 (Avg Bid)
    €149 Keskimäär. tarjous
    5 tarjoukset
    €34 Keskimäär. tarjous
    4 tarjoukset
    €28 Keskimäär. tarjous
    7 tarjoukset

    VHDL implemented in altera de2 board

    €358 (Avg Bid)
    €358 Keskimäär. tarjous
    3 tarjoukset

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    €15 (Avg Bid)
    €15 Keskimäär. tarjous
    2 tarjoukset

    Responsibilities: 1. Engaged in ARM embedded software development (zynq7000 platform development); 2. Debugging WiFi driver and USB driver 3. Build and compile the ke... Build and compile the kernel driver environment 4. Realize the interaction between PS and PL 5. Porting algorithms to embedded platforms (including but not limited to ARM, FPGA, etc.)

    €2146 (Avg Bid)
    €2146 Keskimäär. tarjous
    16 tarjoukset

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

    €23 (Avg Bid)
    €23 Keskimäär. tarjous
    5 tarjoukset

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [kirjaudu nähdäksesi URL:n] Reference Literature: CMOS VLSI Design Happy Bidding

    €242 (Avg Bid)
    €242 Keskimäär. tarjous
    2 tarjoukset

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [kirjaudu nähdäksesi URL:n] Reference Literature: CMOS VLSI Design Happy Bidding

    €137 (Avg Bid)
    €137 Keskimäär. tarjous
    1 tarjoukset

    ...guidelines for the following professional boards: - Accounting Professionals & Ethical Standards Board (APESB) (11 x documents) - Australian Securities & Investments Commission (ASIC) (1 x document) - Australian Taxation Office (ATO) (2 x documents) - Chartered Professional Accountants (CPA) (4 x documents) - Office of Australian Information Commissioner

    €106 (Avg Bid)
    €106 Keskimäär. tarjous
    5 tarjoukset
    FPGA, VDHL coding 4 päivää left
    VARMENNETTU

    Please contact me if you expert In FPGA, VDHL coding

    €1264 (Avg Bid)
    €1264 Keskimäär. tarjous
    13 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €77 (Avg Bid)
    €77 Keskimäär. tarjous
    5 tarjoukset
    €23 Keskimäär. tarjous
    4 tarjoukset

    Verilog simulation of two action-reaction processes

    €26 (Avg Bid)
    €26 Keskimäär. tarjous
    6 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €157 (Avg Bid)
    €157 Keskimäär. tarjous
    7 tarjoukset
    LabView LTC Timecode Encoder/Decoder 3 päivää left
    VARMENNETTU

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

    €304 (Avg Bid)
    €304 Keskimäär. tarjous
    5 tarjoukset

    6 Vhdl questions to solve

    €9 (Avg Bid)
    €9 Keskimäär. tarjous
    1 tarjoukset
    Anyone expert in vhdl 2 päivää left

    Vhdl is needed

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    6 tarjoukset

    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

    €675 (Avg Bid)
    €675 Keskimäär. tarjous
    3 tarjoukset

    Need help program FPGA with Artix-7 using Verliog.

    €110 (Avg Bid)
    €110 Keskimäär. tarjous
    5 tarjoukset

    VHDL, LTE,WiMAX,Bluetooth,RF,FPGA

    €18 / hr (Avg Bid)
    €18 / hr Keskimäär. tarjous
    3 tarjoukset

    I would like a VHDL code that reads 3 txt file and produces 3 txt file. The inputs text files produced by Matlab in binary. please see the attachment for the code I attempted to do but it not working, and text​ input files.

    €63 (Avg Bid)
    €63 Keskimäär. tarjous
    12 tarjoukset

    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

    €3563 (Avg Bid)
    €3563 Keskimäär. tarjous
    21 tarjoukset

    ...with 32 bit instructions and 16 bit data, to be implemented using VHDL. In case of any doubts kindly contact to clarify requirements before making offers. Expectations: - seeking sincere and diligent freelancers. - good understanding and practical experience with digital design using VHDL. - use of Vivado Design Suite (Webpack 2017.4) - aligned and meaningfully

    €262 (Avg Bid)
    €262 Keskimäär. tarjous
    12 tarjoukset

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    €154 (Avg Bid)
    €154 Keskimäär. tarjous
    1 tarjoukset

    Implement the Zen Protocol in the FPGA and update the Mining App

    €1074 (Avg Bid)
    €1074 Keskimäär. tarjous
    3 tarjoukset

    I am looking for a freelancer who can help me with my tax and book keeping management. The chosen person to do this would have to be willing to go BIR and other government offices in order to get the job done.

    €167 (Avg Bid)
    €167 Keskimäär. tarjous
    5 tarjoukset

    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    2 tarjoukset

    I have a Introduction to VLSI Design school course project. I have done most of topics but need to ask a questions and bugs about the project. Need someone to help on this very basic project. Freelancer should known the base sturecture of VLSI lecture. Freelancer either can be student, graduat, postgraduate or more.

    €37 (Avg Bid)
    €37 Keskimäär. tarjous
    8 tarjoukset

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    €447 (Avg Bid)
    €447 Keskimäär. tarjous
    14 tarjoukset

    using VHDL: It’s a simple game of ping pong but only one line using the LED lights. the light will go backward and forward, the player needs to click on control at the edge of last two LED to flip the direction of the LED lights, it will start slow and it will speed up as you play, and the seven segment display will display how many time you hit the

    €12 / hr (Avg Bid)
    €12 / hr Keskimäär. tarjous
    2 tarjoukset

    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    €22 (Avg Bid)
    €22 Keskimäär. tarjous
    6 tarjoukset

    Make a serial interface system using Verilog

    €42 (Avg Bid)
    €42 Keskimäär. tarjous
    4 tarjoukset
    Diseño FPGAs en VHDL Loppuu left
    VARMENNETTU

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas...

    €29 (Avg Bid)
    €29 Keskimäär. tarjous
    1 tarjoukset

    Use a Verilog and Do exactly what is on the paper and hand me a report with codes, synthesized diagrams, and a description comparing the different state assignments

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    7 tarjoukset

    vhdl de 1 board simple project idea

    €23 (Avg Bid)
    €23 Keskimäär. tarjous
    2 tarjoukset
    VHDL questions Loppunut left

    I have some VHDL questions which I nedd to be solved .

    €16 (Avg Bid)
    €16 Keskimäär. tarjous
    5 tarjoukset
    FPGA Designing Loppunut left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    €49 (Avg Bid)
    €49 Keskimäär. tarjous
    14 tarjoukset

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

    €70 / hr (Avg Bid)
    €70 / hr Keskimäär. tarjous
    1 tarjoukset

    Its a small assignment. If you are an expert and have worked on it before. text me

    €114 (Avg Bid)
    €114 Keskimäär. tarjous
    9 tarjoukset
    Project for TIV LAbs 1 päivä left

    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    1 tarjoukset

    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

    €25 (Avg Bid)
    €25 Keskimäär. tarjous
    5 tarjoukset

    ...minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator. * Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT. * Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink

    €205 (Avg Bid)
    €205 Keskimäär. tarjous
    9 tarjoukset
    PLL in VHDL Loppunut left

    Add in our Design a PLL for variable clock speed

    €152 (Avg Bid)
    €152 Keskimäär. tarjous
    12 tarjoukset

    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

    €2025 (Avg Bid)
    €2025 Keskimäär. tarjous
    10 tarjoukset

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    €328 (Avg Bid)
    Mainostettu
    €328 Keskimäär. tarjous
    3 tarjoukset