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    1,844 fpga design projects työtä löytyi, hinnoittelu EUR
    FPGA load Flash 6 päivää left
    VARMENNETTU

    loading a Xilinx SPI flash from external serial source using FPGA

    €487 (Avg Bid)
    €487 Keskimäär. tarjous
    1 tarjoukset

    ...board from Terasic. I am trying to changing the FPGA code DE10-Nano board to add our H/W interface to it. I have trouble to get the correct starting point for the FPGA that will be used with Linux. If you are expert with this board, please help us to provide support to us. Who am I: I am a FPGA design expert, but know nothing about DE10-Nano. I looking

    €25 / hr (Avg Bid)
    €25 / hr Keskimäär. tarjous
    5 tarjoukset
    VHDL FPGA Project 5 päivää left
    VARMENNETTU

    ...the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following a design process as close to the real as possible, but

    €116 (Avg Bid)
    €116 Keskimäär. tarjous
    5 tarjoukset

    i already have the 90% of the code just need to finish 10% and guide me on running the code my my board

    €54 (Avg Bid)
    €54 Keskimäär. tarjous
    7 tarjoukset

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    €87 (Avg Bid)
    €87 Keskimäär. tarjous
    9 tarjoukset

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    €125 (Avg Bid)
    €125 Keskimäär. tarjous
    5 tarjoukset

    ...given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comparing MATLAB result with Xilinx@ System Generator result for above specified 3 images with different

    €122 (Avg Bid)
    €122 Keskimäär. tarjous
    2 tarjoukset

    VHDL implemented in altera de2 board

    €306 (Avg Bid)
    €306 Keskimäär. tarjous
    5 tarjoukset

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    €68 (Avg Bid)
    €68 Keskimäär. tarjous
    3 tarjoukset

    Responsibilities: 1. Engaged in ARM embedded software development (zynq7000 platform development); 2. Debugging WiFi driver and USB driver 3. Build and compile the ke... Build and compile the kernel driver environment 4. Realize the interaction between PS and PL 5. Porting algorithms to embedded platforms (including but not limited to ARM, FPGA, etc.)

    €2140 (Avg Bid)
    €2140 Keskimäär. tarjous
    16 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €77 (Avg Bid)
    €77 Keskimäär. tarjous
    5 tarjoukset

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €155 (Avg Bid)
    €155 Keskimäär. tarjous
    7 tarjoukset

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

    €301 (Avg Bid)
    €301 Keskimäär. tarjous
    5 tarjoukset

    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

    €673 (Avg Bid)
    €673 Keskimäär. tarjous
    3 tarjoukset

    Need help program FPGA with Artix-7 using Verliog.

    €110 (Avg Bid)
    €110 Keskimäär. tarjous
    5 tarjoukset

    VHDL, LTE,WiMAX,Bluetooth,RF,FPGA

    €18 / hr (Avg Bid)
    €18 / hr Keskimäär. tarjous
    3 tarjoukset

    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

    €3553 (Avg Bid)
    €3553 Keskimäär. tarjous
    21 tarjoukset

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    €154 (Avg Bid)
    €154 Keskimäär. tarjous
    1 tarjoukset

    Implement the Zen Protocol in the FPGA and update the Mining App

    €1071 (Avg Bid)
    €1071 Keskimäär. tarjous
    3 tarjoukset

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    €465 (Avg Bid)
    €465 Keskimäär. tarjous
    15 tarjoukset
    FPGA Designing Loppunut left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    €49 (Avg Bid)
    €49 Keskimäär. tarjous
    14 tarjoukset

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

    €70 / hr (Avg Bid)
    €70 / hr Keskimäär. tarjous
    1 tarjoukset

    Its a small assignment. If you are an expert and have worked on it before. text me

    €113 (Avg Bid)
    €113 Keskimäär. tarjous
    9 tarjoukset

    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

    €32 (Avg Bid)
    €32 Keskimäär. tarjous
    1 tarjoukset

    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

    €2019 (Avg Bid)
    €2019 Keskimäär. tarjous
    10 tarjoukset

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    €327 (Avg Bid)
    Mainostettu
    €327 Keskimäär. tarjous
    3 tarjoukset

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    €163 (Avg Bid)
    €163 Keskimäär. tarjous
    8 tarjoukset

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    €132 (Avg Bid)
    €132 Keskimäär. tarjous
    6 tarjoukset

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

    €344 (Avg Bid)
    €344 Keskimäär. tarjous
    2 tarjoukset

    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

    €268 (Avg Bid)
    €268 Keskimäär. tarjous
    8 tarjoukset

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

    €123 (Avg Bid)
    €123 Keskimäär. tarjous
    2 tarjoukset

    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [kirjaudu nähdäksesi URL:n] I want video to

    €139 (Avg Bid)
    €139 Keskimäär. tarjous
    4 tarjoukset

    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis

    €165 (Avg Bid)
    €165 Keskimäär. tarjous
    9 tarjoukset

    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

    €19 (Avg Bid)
    €19 Keskimäär. tarjous
    12 tarjoukset

    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

    €126 (Avg Bid)
    €126 Keskimäär. tarjous
    3 tarjoukset
    D Class Amp Loppunut left

    Design of a D class amp. Digital Input to DAC from FPGA . VHDL files for Digital Input will be provides. Amplification part of the circuit to have a Mosfet setup. DAC and Mosfets have been selected. Full circuit simulation to be done in Tina software.

    €232 (Avg Bid)
    €232 Keskimäär. tarjous
    11 tarjoukset

    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

    €205 (Avg Bid)
    €205 Keskimäär. tarjous
    3 tarjoukset
    ProjectDone Loppunut left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

    €16 / hr (Avg Bid)
    €16 / hr Keskimäär. tarjous
    12 tarjoukset
    abiramiamanm Loppunut left

    vlsi coding using QUARTUS II software FPGA

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    3 tarjoukset

    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

    €2934 (Avg Bid)
    €2934 Keskimäär. tarjous
    11 tarjoukset

    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

    €200 (Avg Bid)
    €200 Keskimäär. tarjous
    2 tarjoukset
    Digital To Analoge Loppunut left

    ...Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation can be done in Tina software. An explanation of the VHDL code to be supplied so that

    €89 (Avg Bid)
    €89 Keskimäär. tarjous
    2 tarjoukset

    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

    €39 (Avg Bid)
    €39 Keskimäär. tarjous
    4 tarjoukset

    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

    €213 (Avg Bid)
    €213 Keskimäär. tarjous
    4 tarjoukset

    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

    €551 (Avg Bid)
    €551 Keskimäär. tarjous
    9 tarjoukset

    We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)

    €322 (Avg Bid)
    €322 Keskimäär. tarjous
    9 tarjoukset

    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

    €121 (Avg Bid)
    €121 Keskimäär. tarjous
    7 tarjoukset

    ...be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....

    €95 (Avg Bid)
    €95 Keskimäär. tarjous
    1 tarjoukset

    ...be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....

    €349 (Avg Bid)
    €349 Keskimäär. tarjous
    3 tarjoukset

    ...player's movement should not be pixel by pixel but rather, it should keep sliding until it hits the wall(boundary). The movement control should be done through the keys on the FPGA. The maze should have a fully functional non-flickering background, which should be easily be replaced. It should also have a start and game over screen. The work should have

    €153 (Avg Bid)
    €153 Keskimäär. tarjous
    4 tarjoukset