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    2,815 e1 verilog työtä löytyi, hinnoittelu EUR

    My project is simple , I just need some with a high knowledge in Verilog Simulator Program , The project has only two questions , one about program four numbers to act like "DIGITAL CLOCK". Two numbers on the left will display the hours (00 to 12), the other two numbers will display the minutes (00 to 59). The other about to write a Verilog code that produces at least four different dyn...

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    €33 Keskimäär. tarjous
    2 tarjoukset
    PHP Laravel 5 päivää left
    VARMENNETTU

    We're looking for a PHP Laravel expert to help us solve a recurrent issue happening in our iOS and Android mobile applications. The error is: ErrorException: file_put_contents(/var/www/html/admin-panel/storage/framework/cache/data/8c/e1/8ce10ae1d8197075990151229fdfc0741463cd5d): failed to open stream: No such file or directory If you have encountered AND SOLVED this issue before, we'r...

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    €34 Keskimäär. tarjous
    21 tarjoukset
    RSR5 Scheme Language 5 päivää left
    VARMENNETTU

    ;; Towards a Scheme Interpreter for the Lambda Calculus -- Part 1: Syntax ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; All programming is to be carried out using the pure functional sublanguage of R5RS Scheme. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; You might want to have a look at [...

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    €48 Keskimäär. tarjous
    2 tarjoukset

    Need help with a small problem using Logic Gates/System Verilog

    €18 (Avg Bid)
    €18 Keskimäär. tarjous
    6 tarjoukset
    need vhdl /verilog expert 5 päivää left
    VARMENNETTU

    i need help in project . I am searching of vhdl expert. Bid any one who knows vhdl code and help me in project

    €19 (Avg Bid)
    €19 Keskimäär. tarjous
    5 tarjoukset

    I will be implementing this on vivado 2019, with using the zynq xc7z020-1clg400c chip Reaction Time Monitor Create a Reaction Time Monitor (RTM) that can indicate how quickly an user can respond to a stimulus. In operation, the RTM is initialized when a “start” button is pressed. Immediately after the start button is pressed, the 7seg display is set to show all 0’s, and then a r...

    €28 (Avg Bid)
    €28 Keskimäär. tarjous
    7 tarjoukset

    I will be implementing this on vivado 2019, with using the zynq xc7z020-1clg400c chip Stopwatch with Start, Stop, Increment, and Clear Functionality Create a four-digit stopwatch on your Blackboard, using the seven-segment display as an output device. The stopwatch should count from 0.000 to 9.999 seconds and then roll over, with the count value updating exactly once per millisecond. The stopwatc...

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    3 tarjoukset

    I will be implementing this on Vivado 2019 using a zynq xc7z020-1clg400c chip. 1. Create a Parameterized Counter Design a parameterized binary counter module that counts from zero to a value given as a parameter, and then resets to zero. Include a count enable input cen that enables counting only when asserted. In the example module definition below, a second parameter WIDTH is defined because th...

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    €200 Keskimäär. tarjous
    5 tarjoukset
    Verilog code in vivado 4 päivää left

    Verilog code for 8 bit radix-4 booth (modified booth)algorithm with its test bench and waveform

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    €25 Keskimäär. tarjous
    3 tarjoukset

    I need you to develop some software for me. I would like this software to be developed for Windows.

    €35 (Avg Bid)
    €35 Keskimäär. tarjous
    2 tarjoukset

    I need help with building 5 tasks in Verilog. Simple tasks.

    €33 (Avg Bid)
    €33 Keskimäär. tarjous
    1 tarjoukset
    verilog language 2 päivää left

    its a project about Verilog language, we need knowledge for theory as well.

    €51 (Avg Bid)
    €51 Keskimäär. tarjous
    13 tarjoukset
    Implement Verilog Design for given C code 2 päivää left
    VARMENNETTU

    If you are fluent in Verilog and C, message me for further details

    €122 (Avg Bid)
    €122 Keskimäär. tarjous
    13 tarjoukset

    I transferred a project over from Xilinx to Quartus. But it is giving me some minor syntax errors that I don't have the time to fix. Message me for details.

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    €32 Keskimäär. tarjous
    4 tarjoukset

    I have a project, which requires verilog coding. The flowchart posted in files, needs to be implemented through Verilog.

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    3 tarjoukset

    Our client a leading semiconductor based in Europe are seeking an IC Physical Design Engineer for a minimum 6 month project This project will be fully remote for the duration. Skills/Experience - Digital Back End design flow Cadence/Synopsis Circuit/Physical Design Place & Route Experience with UNIX Scripting Perl, Python, Bash RTL architecture synthesis VHDL/Verilog - Digital Circui...

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    €43 / hr Keskimäär. tarjous
    13 tarjoukset

    System Verilog based AES implementation using Modelsim software is required. The project has to be completed within 2 days and instructor codes and notes are available to help with the coding. Please inbox me for more details and the codes to help in implementation. Freelancers with lower bidding will be preferred and my maximum budget is 80 dollars

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    €114 Keskimäär. tarjous
    6 tarjoukset

    I would like this done on Vivado 2019, I have more details of the project if accepted (as well as the chip I'm using) 1. Create a VGA IP and connect it to the Real Digital’s HDMI IP to display solid square on the screen using HDMI Develop a VGA display controller that syncs at 720p (1280x720@60Hz). To get the timing necessary for this resolution you will need to used the clocking wizar...

    €256 (Avg Bid)
    €256 Keskimäär. tarjous
    5 tarjoukset

    I am looking for a lawyer for E1 treaty trade Visa (from UK to US) application

    €13 / hr (Avg Bid)
    €13 / hr Keskimäär. tarjous
    2 tarjoukset

    I am looking for someone who can design FPGA mining bitstreams . I'm looking for someone who can work with me long term , and maybe arrange future employment . Please apply only if you are europe based ( i dont want any pakistan / india , sorry I had bad experiences in the past . The short version of this project is that I want to mine SCRYPT algo on NICEHASH , using a BCU 1525 FPGA. I also ...

    €1149 (Avg Bid)
    €1149 Keskimäär. tarjous
    2 tarjoukset

    very good knowledge of the verilog labguage and should be able to write verilog code and modify it according to Synopsys Design Compiler, Design Compiler and IC Compiler

    €92 (Avg Bid)
    €92 Keskimäär. tarjous
    3 tarjoukset

    In this project, A and B are digital signals, while VOUT is an analog output signal. You are required to.1. Design Verilog block to generate waveforms as shown in the following figure.2. Design analog block acting as a NAND gate to generate “VOUT”. Simulate and verify your design.

    €80 (Avg Bid)
    €80 Keskimäär. tarjous
    9 tarjoukset

    Urgent Verilog FSM help required

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    9 tarjoukset

    As a Software developer, I need a serious and kind web developer to convert Figma landing pages to Responsive Bootstrap HTML Landing page (LP-1 AND LP-2) and Email: E1 (Coming Soon), E2 (What is costar), E3 (Who its for), E4 (global Canada) pages. Link: [kirjaudu nähdäksesi URL:n]

    €35 (Avg Bid)
    €35 Keskimäär. tarjous
    12 tarjoukset

    Need an expert in system verilog

    €13 (Avg Bid)
    €13 Keskimäär. tarjous
    3 tarjoukset

    Change MATLAB code for image processing to verilog code.

    €21 (Avg Bid)
    €21 Keskimäär. tarjous
    2 tarjoukset

    i want long term employee. i have matlab code. need to convert one simple class to verilog. its own and plagiarism free work is needed. if you are expert, please bid here

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    €2 / hr Keskimäär. tarjous
    5 tarjoukset

    I need a computer and digital design expert to help in some projects using Verilog and C preferable

    €81 (Avg Bid)
    €81 Keskimäär. tarjous
    13 tarjoukset

    Its a digital system design homework using Altera’s Quartus II V13.0-SP1, and develop a Random Number Generator which will display random decimal numbers on the 7 segment displays of the DE2 board... It may includes ASM charts, verilog code, and simulation NOTE: need only assignment 1 mentioned in the attached word file.

    €22 (Avg Bid)
    €22 Keskimäär. tarjous
    3 tarjoukset

    This will be implemented on Vivado 2019 1. Design and implement a PWM IP block Create a PWM block in Verilog that uses a 10-bit value to set the duty cycle, and use the 10 slide switches for input. Your circuit can use Blackboard’s 100MHz FPGA clock, so with a 10-bit resolution, you can use up to a 100KHz pulse frequency (by setting the “PWM frequency” divider value in the figur...

    €132 (Avg Bid)
    €132 Keskimäär. tarjous
    5 tarjoukset

    i want long term employee. i have matlab code. need to convert one simple class to verilog. its own and plagiarism free work is needed. if you are expert, please bid here

    €3 / hr (Avg Bid)
    €3 / hr Keskimäär. tarjous
    2 tarjoukset

    I am looking for someone who can design FPGA mining bitstreams . I'm looking for someone who can work with me long term , and maybe arrange future employment . Please apply only if you are europe based ( i dont want any pakistan / india , sorry I had bad experiences in the past . The short version of this project is that I want to mine SCRYPT algo on NICEHASH , using a BCU 1525 FPGA. I also ...

    €1045 (Avg Bid)
    €1045 Keskimäär. tarjous
    3 tarjoukset

    I want to implement the Gaussian Sampler in Verilog

    €96 (Avg Bid)
    €96 Keskimäär. tarjous
    3 tarjoukset

    I've finished a project on RSA in Verilog and implemented it on FPGA (Zybo), but I need help to optimize it in speed and area on the FPGA. So it will not take a lot of time for an expert in hardware to find some flaws in my design to optimize it according the two parameters stated above. The implementation only consists of an high precision adder and multiplier in Verilog (1028 bit). In summa...

    €117 (Avg Bid)
    €117 Keskimäär. tarjous
    6 tarjoukset

    Hi. I want to make multi function calculator with verilog that can display on lcd screen using ISE design suit , Spartan3 XC3S200 functions like +,-,*,/ needed also need a description of the function how they are working

    €66 (Avg Bid)
    €66 Keskimäär. tarjous
    4 tarjoukset

    Write verilog code to implement algorithm on FPGA I have MATLAB code for the same algorithm.

    €24 (Avg Bid)
    €24 Keskimäär. tarjous
    7 tarjoukset
    6-bit multiplier Loppunut left

    Modify the multiplier in the picture from 4-bit multiplier to be 6-bit multiplier and write Verilog code for the new multiplier. Verify the design with simulation.

    €16 (Avg Bid)
    €16 Keskimäär. tarjous
    5 tarjoukset

    We are a medical device company located in Israel. Our product does data acquisition of brain signals, processes them and provides valuable information to the Neurosergian. We need an FPGA designer to work with us in coding the verilog of a new board. The designer must have experience in programming FPGA that control systems that has Analog to Digital Converters and serial interfaces (SPI, LV...

    €880 (Avg Bid)
    €880 Keskimäär. tarjous
    18 tarjoukset

    Our main goal to minimize the BW in client side with good quality of voice . We need some kind of bandwidth compression system ( upto 60-80% than usual SIP calls )from Server A to Server B. Server A = Asterisk server Server B = Asterisk Client server Explanation of scenario: 1. server A ( asterisk server, with static IP) receiving VoIP calls , with sip protocol, using G711,G729 and/or G723.1...

    €464 (Avg Bid)
    €464 Keskimäär. tarjous
    4 tarjoukset

    Urgent Verilog FSM help required

    €17 (Avg Bid)
    €17 Keskimäär. tarjous
    10 tarjoukset

    you have to write the verilog code using Quartus software and show your output on waveforms

    €26 (Avg Bid)
    €26 Keskimäär. tarjous
    9 tarjoukset
    Trophy icon Verilog design Loppunut left

    Verilog design for a small project

    €17 (Avg Bid)
    €17
    2 työtä
    Lighting Pattern Loppunut left

    I need to create a Verilog code for a DE0 board. The Verilog code is supposed to display a lighting pattern on the DE0 board, when switched on. The code must include a Finite State Machine. Attached are the pin assignments.

    €15 (Avg Bid)
    €15 Keskimäär. tarjous
    3 tarjoukset

    Job Description :-   We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs.  The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic...

    €292 (Avg Bid)
    Mainostettu
    €292 Keskimäär. tarjous
    13 tarjoukset

    we have to code in verilog for mini stereo digital circuit with given specs

    €128 (Avg Bid)
    €128 Keskimäär. tarjous
    13 tarjoukset

    Problem 1 [9pt] Consider the following C program: int SumOfSquares(int n) { if (n <= 0) return 0; else return n*n+SumOfSquares(n-1); } a) (5pt) Write down a tail recursive implementation of function SumOfSquares in C language. You can use helper function in your solution. b) (4pt) An “optimizing” compiler will often be able to generate efficient code for recursive functions when t...

    €49 (Avg Bid)
    €49 Keskimäär. tarjous
    4 tarjoukset

    I am looking for Electronic Engineer with Xilinx, Verilog, Altium experiences. I am also Engineer, but I need partner. Thanks.

    €15 / hr (Avg Bid)
    €15 / hr Keskimäär. tarjous
    15 tarjoukset

    Problem 1 [9pt] Consider the following C program: int SumOfSquares(int n) { if (n <= 0) return 0; else return n*n+SumOfSquares(n-1); } a) (5pt) Write down a tail recursive implementation of function SumOfSquares in C language. You can use helper function in your solution. b) (4pt) An “optimizing” compiler will often be able to generate efficient code for recursive functions when the...

    €13 (Avg Bid)
    €13 Keskimäär. tarjous
    10 tarjoukset

    a small Mips CPU in verilog. component file are providied.

    €11 (Avg Bid)
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    1 tarjoukset